公开(公告)号：US11748035B2

公开(公告)日：2023-09-05

申请号：US17409495

申请日：2021-08-23

申请人： Micron Technology, Inc.

发明人： Gary L. Howe

IPC分类号： G06F3/00 ,  G11C11/00 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  B24D18/00 ,  B32B3/30 ,  B32B13/06 ,  E21B10/567 ,  E21B10/573 ,  G11C11/4076 ,  G11C8/12

CPC分类号： G06F3/0659 ,  B24D18/0009 ,  B32B3/30 ,  B32B13/06 ,  E21B10/567 ,  E21B10/5735 ,  G06F3/0604 ,  G06F3/0673 ,  G11C7/109 ,  G11C7/1045 ,  G11C11/4087 ,  G11C11/4096 ,  B32B2307/308 ,  B32B2307/554 ,  B32B2307/558 ,  B32B2307/704 ,  G11C8/12 ,  G11C11/4076 ,  Y10T428/24479 ,  Y10T428/24612 ,  Y10T428/26

摘要： A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

公开(公告)号：US11513945B2

公开(公告)日：2022-11-29

申请号：US17181718

申请日：2021-02-22

申请人： Micron Technology, Inc.

发明人： Daniel B. Penney ,  Gary L. Howe

IPC分类号： G06F12/02 ,  G06F12/0855 ,  G06F13/16

摘要： The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US11132142B2

公开(公告)日：2021-09-28

申请号：US17063463

申请日：2020-10-05

申请人： Micron Technology, Inc.

发明人： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC分类号： G11C7/20 ,  G06F3/06 ,  G11C11/4072 ,  G11C8/04 ,  G11C7/10 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

摘要： A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.

公开(公告)号：US20210019075A1

公开(公告)日：2021-01-21

申请号：US17063463

申请日：2020-10-05

申请人： Micron Technology, Inc.

发明人： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC分类号： G06F3/06 ,  G11C11/4072 ,  G11C7/20 ,  G11C8/04 ,  G11C7/10 ,  G06F11/10

摘要： A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.

公开(公告)号：US10825491B2

公开(公告)日：2020-11-03

申请号：US15837666

申请日：2017-12-11

申请人： Micron Technology, Inc.

发明人： Byung S. Moon ,  Gary L. Howe ,  Harish N. Venkata ,  David R. Brown

IPC分类号： G11C7/10 ,  G11C11/4072 ,  G11C8/04 ,  G11C11/408 ,  G11C7/20 ,  G06F12/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

摘要： A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.

公开(公告)号：US10795603B2

公开(公告)日：2020-10-06

申请号：US16555852

申请日：2019-08-29

申请人： Micron Technology, Inc.

发明人： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC分类号： G06F3/06 ,  G11C11/4072 ,  G11C7/20 ,  G11C8/04 ,  G11C7/10 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C29/46

摘要： A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US20200044640A1

公开(公告)日：2020-02-06

申请号：US16050978

申请日：2018-07-31

申请人： Micron Technology, Inc.

发明人： Gary L. Howe ,  Jeffrey E. Koelling

IPC分类号： H03K5/156 ,  H03K5/159 ,  G11C7/22

摘要： The present disclosure relates generally to improved systems and methods for control of one or more timing signals in a memory device. More specifically, the present disclosure relates to configurable duty cycle correction at one or more DQ pins (e.g., data input/output (I/O) pins) of the memory device. For example, the memory device may include a configurable phase splitter and/or selective capacitive loading circuitry implemented to adjust the duty cycle of a timing signal at one or more DQ pins during and/or after manufacture of the memory device. Accordingly, the memory device may include increased flexibility and granularity of control over the one or more timing signals.

公开(公告)号：US20190384526A1

公开(公告)日：2019-12-19

申请号：US16555852

申请日：2019-08-29

申请人： Micron Technology, Inc.

发明人： Byung S. Moon ,  Harish N. Venkata ,  Gary L. Howe ,  Myung Ho Bae

IPC分类号： G06F3/06 ,  G11C11/4072

摘要： A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.

公开(公告)号：US20190179552A1

公开(公告)日：2019-06-13

申请号：US15837666

申请日：2017-12-11

申请人： Micron Technology, Inc.

发明人： Byung S. Moon ,  Gary L. Howe ,  Harish N. Venkata ,  David R. Brown

IPC分类号： G06F3/06 ,  G11C11/4072 ,  G11C11/4091

摘要： A memory device may include a memory array, which may also include, multiple memory cells. The memory device may also include one or more counters designed to generate internal memory addresses to sequentially access the memory cells and facilitate writing logical zeros to all of the memory cells.

公开(公告)号：US20220391334A1

公开(公告)日：2022-12-08

申请号：US17882550

申请日：2022-08-06

申请人： Micron Technology, Inc.

发明人： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC分类号： G06F13/16 ,  G11C11/406 ,  G11C11/4096

摘要： Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.