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    MULTI-LEVEL CELL AND MULTI-SUB-BLOCK PROGRAMMING IN A MEMORY DEVICE
    42.
    发明公开
    MULTI-LEVEL CELL AND MULTI-SUB-BLOCK PROGRAMMING IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230207019A1

    公开(公告)日：2023-06-29

    申请号：US18081114

    申请日：2022-12-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Lawrence Celso Miranda ,  Sheyang Ning ,  Jeffrey S. McNeil ,  Tomoko Ogura Iwasaki

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/24

    Abstract: Control logic in a memory device causes a boost voltage to be applied one or more times to a plurality of unselected wordlines of a block of the memory array, the block comprising a plurality of sub-blocks, and the boost voltage to boost a channel potential of each of the plurality of sub-blocks by an amount each time the boost voltage is applied. The control logic further selectively discharges the amount of boost voltage from one or more of the plurality of sub-blocks after each time the boost voltage is applied according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. Additionally, the control logic causes a single programming pulse to be applied to one or more selected wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE
    44.
    发明公开
    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230145358A1

    公开(公告)日：2023-05-11

    申请号：US17978890

    申请日：2022-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/064

    Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

    OVERWRITING AT A MEMORY SYSTEM
    45.
    发明申请
    OVERWRITING AT A MEMORY SYSTEM 有权

    公开(公告)号：US20230060859A1

    公开(公告)日：2023-03-02

    申请号：US17462305

    申请日：2021-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan S. Parry ,  Jeffrey S. McNeil ,  Giuseppe Cariello ,  Kishore Kumar Muchherla ,  Reshmi Basu

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

    Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.

    MEMORY DEVICES FOR MULTILPLE READ OPERATIONS
    46.
    发明申请
    MEMORY DEVICES FOR MULTILPLE READ OPERATIONS 有权

    公开(公告)号：US20220189517A1

    公开(公告)日：2022-06-16

    申请号：US17463789

    申请日：2021-09-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

    IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    APPARATUS AND METHODS FOR DISCHARGING CONTROL GATES AFTER PERFORMING AN ACCESS OPERATION ON A MEMORY CELL
    47.
    发明申请
    APPARATUS AND METHODS FOR DISCHARGING CONTROL GATES AFTER PERFORMING AN ACCESS OPERATION ON A MEMORY CELL 有权

    公开(公告)号：US20200152272A1

    公开(公告)日：2020-05-14

    申请号：US16186677

    申请日：2018-11-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jeffrey S. McNeil

    IPC: G11C16/08 ,  G11C16/04

    Abstract: Methods, and apparatus configured to perform similar methods, might include performing an access operation on a memory cell of an array of memory cells, discharging a control gate of a first field-effect transistor after performing the access operation, discharging a control gate of a second field-effect transistor connected in series between the first field-effect transistor and the memory cell after discharging the control gate of the first field-effect transistor, and discharging a control gate of the memory cell after discharging the control gate of the second field-effect transistor.

    Concurrent slow-fast memory cell programming
    49.
    发明授权
    Concurrent slow-fast memory cell programming 有权

    公开(公告)号：US12211552B2

    公开(公告)日：2025-01-28

    申请号：US18121846

    申请日：2023-03-15

    Applicant: Micron Technology, Inc.

    Inventor： Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Sheyang Ning ,  Jeffrey S. McNeil

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

    Abstract: Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.

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