公开(公告)号：US20240045617A1

公开(公告)日：2024-02-08

申请号：US17883191

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604

Abstract: Methods, systems, and devices for address verification at a memory system are described. A memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. For example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. The memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. The address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.

公开(公告)号：US11775207B2

公开(公告)日：2023-10-03

申请号：US17651214

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688

Abstract: Methods, systems, and devices for techniques to perform a write operation are described. In response to receiving a sequential write command from a host system, the memory system may determine non-linear offsets for a set of requests for portions of the data. The memory system may determine a first subset of the data that includes data segments having logical addresses with gaps corresponding to the offset between the data segments to store in a first memory device. The memory system may store the first subset in a buffer and program the first subset to the first memory device. Additionally, the memory system may determine a second subset of data that using the offset and may transmit a second set of requests for the second subset of data, which may be stored in the buffer and programmed to a second memory device.

公开(公告)号：US20230305617A1

公开(公告)日：2023-09-28

申请号：US18096288

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Marco Onorato ,  Roberto IZZI ,  Stephen Hanna ,  Jonathan S. Parry ,  Reshmi Basu ,  Nadav Grosz ,  David Aaron Palmer

IPC: G06F1/3234 ,  G06F9/4401 ,  G06F1/324

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F9/4411

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

公开(公告)号：US11513835B2

公开(公告)日：2022-11-29

申请号：US16889029

申请日：2020-06-01

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Kulachet Tanpairoj ,  Stephen Hanna

IPC: G06F9/48 ,  G06F12/08 ,  G06F12/0875

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

公开(公告)号：US20220276970A1

公开(公告)日：2022-09-01

申请号：US17748595

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F12/14 ,  G06F11/10 ,  G06F21/79 ,  H04L9/08 ,  G06F12/02 ,  G11C16/14 ,  G06F21/60 ,  H03M13/11

Abstract: A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

公开(公告)号：US11294585B2

公开(公告)日：2022-04-05

申请号：US17129087

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.