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公开(公告)号：US11127481B1
公开(公告)日：2021-09-21
申请号：US16926167
申请日：2020-07-10
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhongguang Xu , Zhenming Zhou
Abstract: A value corresponding to an operating characteristic of a memory sub-system is determined. The value is compared to a first threshold level to determine whether a first condition is satisfied. The value is also compared to a second threshold level to determine whether a second condition is satisfied. In response to satisfying the first condition, a read scrub operation associated with the memory sub-system is executed. In response to satisfying the second condition, a write scrub operation associated with the memory sub-system is executed.
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公开(公告)号：US20250053326A1
公开(公告)日：2025-02-13
申请号：US18933274
申请日：2024-10-31
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu
IPC: G06F3/06
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.
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公开(公告)号：US12210752B2
公开(公告)日：2025-01-28
申请号：US18372998
申请日：2023-09-26
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Jian Huang , Tingjun Xie , Murong Lang , Zhenming Zhou
IPC: G06F3/06
Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.
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公开(公告)号：US20240428865A1
公开(公告)日：2024-12-26
申请号：US18745615
申请日：2024-06-17
Applicant: Micron Technology, Inc.
Inventor： Hanping Chen , Zhongguang Xu
Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a first word line in the array of memory cells during a read operation on the first word line, and apply a bit line bias to a number of bit lines coupled to the first word line during the read operation on the first word line, wherein the bit line bias includes a bit line bias offset associated with performing the read operation on a partially programmed block.
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公开(公告)号：US12176060B2
公开(公告)日：2024-12-24
申请号：US18531003
申请日：2023-12-06
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Zhongguang Xu , Jiangli Zhu
IPC: G11C7/10
Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
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Patent Agency Ranking
公开(公告)号：US20240370364A1
公开(公告)日：2024-11-07
申请号：US18633288
申请日：2024-04-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Zhongguang Xu , Peng Zhang , Zhenming Zhou
IPC: G06F12/02
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: identifying a block of the memory device, the block spanning over a plurality of decks; determining whether a set of memory cells of the memory device is disposed in a first deck of the block or a second deck of the block, the first deck having a memory reliability metric satisfying a first criterion pertaining to a reliability of a deck, and the second deck having a memory reliability metric not satisfying the first criterion; selecting, based on the determination, an erase policy for performing an erase operation with respect to the set of memory cells; and causing the erase operation to be performed with respect to the set of memory cells in accordance with the erase policy.
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公开(公告)号：US20240312526A1
公开(公告)日：2024-09-19
申请号：US18670073
申请日：2024-05-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhongguang Xu , Tingjun Xie , Murong Lang
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3404
Abstract: A processing device in a memory sub-system logically closes a block of a memory device to prevent additional program operations from being performed on the block. The processing device further causes one or more wordlines of the block to be programmed with padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was logically closed. In addition, the processing device causes a remaining set of wordlines of the block to be concurrently programmed to a single program state.
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公开(公告)号：US20240176508A1
公开(公告)日：2024-05-30
申请号：US18521458
申请日：2023-11-28
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Zhongguang Xu , Ronit Roneel Prakash , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679
Abstract: A system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.
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公开(公告)号：US20240105240A1
公开(公告)日：2024-03-28
申请号：US18531003
申请日：2023-12-06
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Zhongguang Xu , Jiangli Zhu
IPC: G11C7/10
CPC classification number: G11C7/1063
Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
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公开(公告)号：US20240020025A1
公开(公告)日：2024-01-18
申请号：US18372998
申请日：2023-09-26
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Jian Huang , Tingjun Xie , Murong Lang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0679 , G06F3/0655
Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.
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