Abstract:
An apparatus comprising a drive array, a first cache circuit, a plurality of second cache circuits and a controller. The drive array may comprise a plurality of disk drives. The plurality of second cache circuits may each be connected to a respective one of the disk drives. The controller may be configured to (i) control read and write operations of the disk drives, (ii) read and write information from the disk drives to the first cache, (iii) read and write information to the second cache circuits, and (iv) control reading and writing of information directly from one of the disk drives to one of the second cache circuits.
Abstract:
An apparatus comprising a storage array, a primary controller, a secondary controller and a solid state device. The storage array may be configured to be accessed by a plurality of controllers. A first of the plurality of the controllers may be configured as the primary controller configured to read and write to and from the storage array during a normal condition. A second of the plurality of the controllers may be configured as the secondary controller configured to read and write to and from the storage array during a fault condition. The solid state device may be configured to (i) store data and (ii) be accessed by the storage array and the secondary controller.
Abstract:
An apparatus and method to dynamically allocate cache in a SAN controller between a first fixed cache comprising traditional RAID cache comprised of RAM and a second, scalable RAID cache comprising of SSDs (Solid State Devices). The method is dynamic and switches between the first and second cache depending on IO demand.
Abstract:
A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.
Abstract:
A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.
Abstract:
An interrupt signal indicating the existence of a bus configuration error within a disk array system is generated by monitoring the enable signals controlling bus drivers included in the array system. The array configuration error detector includes bus configuration error detection logic for each multiple-source bus within the array. Each bus configuration error detector is connected to receive all enable signals for the bus drivers associated with one bus and decode the received enable signals to generate an error signal when more than one of the received enable signals is active. The error signals generated for each of the multiple-source busses are provided to an adder and combined to form the configuration error interrupt signal for the array.
Abstract:
A method for establishing a secure connection between a first computer and a second computer, comprising the steps of (A) generating a signature authentication pair on the first computer, (B) receiving a plurality of authentication pairs that may or may not include the signature authentication pair, (C) detecting whether the signature authentication pair is received in the authentication pairs and (D) if the signature authentication pair is detected, creating a secure connection between the first computer and the second computer.
Abstract:
An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.
Abstract:
An apparatus comprising a remote storage array, a primary storage array and a network. The remote storage array may be configured to (i) define a queue size based on a performance capability of the remote storage array, (ii) generate a multiplier based on resources being used by the remote storage array, and (iii) adjust the queue size by the multiplier. The primary storage array may be configured to execute input/output (IO) requests between the remote storage array and the primary storage array based on the adjusted queue size. The network may be configured to connect the remote storage array to the primary storage array.
Abstract:
An apparatus comprising an interface, a first port, and a second port. The interface may be configured to connect to a host computer. The first port may be configured to connect to a first set of storage devices using a first protocol. The second port may be configured to connect to a second set of storage devices using a second protocol. The apparatus may provide support for the first protocol and the second protocol to allow communication using both the first protocol and the second protocol through the interface.