公开(公告)号：US20120135356A1

公开(公告)日：2012-05-31

申请号：US13359791

申请日：2012-01-27

申请人： Makoto Sakuma ,  Takuya Futatsuyama

发明人： Makoto Sakuma ,  Takuya Futatsuyama

IPC分类号： G03F7/20

CPC分类号： G11C5/063 ,  H01L27/0207 ,  H01L27/105

摘要： A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

摘要翻译： 半导体器件包括存储单元阵列区域，存储单元阵列区域的外围的外围电路区域和存储单元阵列区域与外围电路区域之间具有特定宽度的边界区域，存储单元阵列区域包括 包括非易失性半导体存储单元的单元区域，从单元区域的内部延伸到单元区域外的线性布线，以及比边界区域中的线性布线更下层的布线，并且电连接到线性布线， 并且下层布线的布线宽度大于线性布线的宽度，外围电路区域包括经由下层布线电连接到线性布线的图案，不能设置线性布线的边界区域和布线 与线性配线相同。

公开(公告)号：US07728435B2

公开(公告)日：2010-06-01

申请号：US12143597

申请日：2008-06-20

申请人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

发明人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

IPC分类号： H01L23/485

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

摘要翻译： 一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。 该装置还包括上接触孔，下接触孔和接触塞。 上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。 底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。 下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。 下接触孔的上部具有与沟槽相同的宽度。 接触塞设置在上接触孔和下接触孔中。

公开(公告)号：US07701742B2

公开(公告)日：2010-04-20

申请号：US11851078

申请日：2007-09-06

申请人： Makoto Sakuma ,  Takuya Futatsuyama

发明人： Makoto Sakuma ,  Takuya Futatsuyama

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C16/04

CPC分类号： G11C5/063 ,  H01L27/0207 ,  H01L27/105

摘要： A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

摘要翻译： 半导体器件包括存储单元阵列区域，存储单元阵列区域的外围的外围电路区域和存储单元阵列区域与外围电路区域之间具有特定宽度的边界区域，存储单元阵列区域包括 包括非易失性半导体存储单元的单元区域，从单元区域的内部延伸到单元区域外的线性布线，以及比边界区域中的线性布线更下层的布线，并且电连接到线性布线， 并且下层布线的布线宽度大于线性布线的宽度，外围电路区域包括经由下层布线电连接到线性布线的图案，不能设置线性布线的边界区域和布线 与线性配线相同。

公开(公告)号：US07679108B2

公开(公告)日：2010-03-16

申请号：US11339483

申请日：2006-01-26

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma

IPC分类号： H01L27/10

CPC分类号： H01L27/11517 ,  G11C16/30 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory includes a plurality of active regions; a plurality of bit line contacts disposed on respective active regions; a plurality of first local lines formed in an island shape and in contact with upper surfaces of the plurality of bit line contacts; a plurality of first via contacts in contact with the upper surfaces of the plurality of first local lines and aligned in a direction parallel to the active regions; a first bit line in contact with one of the plurality of first via contacts and extending in a direction parallel to the active regions; and a plurality of second via contacts arranged above the first via contacts that are not in contact with the first bit line through respective second local lines.

摘要翻译： 半导体存储器包括多个有源区; 布置在相应的有源区上的多个位线触点; 形成为岛状且与多个位线接触件的上表面接触的多个第一局部线; 多个第一通孔触点，与所述多个第一局部线的上表面接触并且在与所述有源区域平行的方向上对齐; 与所述多个第一通孔接触中的一个接触并沿平行于所述有源区域的方向延伸的第一位线; 以及多个第二通孔接触件，其布置在第一通孔接触件之上，所述第一通孔接头不通过相应的第二本地线路与第一位线接触。

公开(公告)号：US20090209733A1

公开(公告)日：2009-08-20

申请号：US12293541

申请日：2007-03-20

申请人： Akira Otsuka ,  Makoto Sakuma

发明人： Akira Otsuka ,  Makoto Sakuma

IPC分类号： C07K16/28

CPC分类号： C07K16/2863 ,  A61K2039/505

摘要： A therapeutic agent for rheumatoid arthritis, particularly a therapeutic agent for ameliorating an inflammatory symptom or bone deformity in rheumatoid arthritis, which comprises an antibody that binds to a hepatocyte growth factor receptor as an active ingredient.

摘要翻译： 用于类风湿性关节炎的治疗剂，特别是用于改善类风湿性关节炎的炎性症状或骨畸形的治疗剂，其包含结合肝细胞生长因子受体作为有效成分的抗体。

公开(公告)号：US07534682B2

公开(公告)日：2009-05-19

申请号：US11582015

申请日：2006-10-16

申请人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma

发明人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： G11C16/0433 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a second element isolating region and includes a second gate insulating film and a second gate electrode. The upper part of the first and second element isolating regions project from a semiconductor substrate and their corners are curved. The width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region is equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.

摘要翻译： 半导体存储器件包括第一和第二MOS晶体管。 第一MOS晶体管形成在由第一元件隔离区域包围的区域中，并且包括第一栅极绝缘膜和第一栅极电极。 第二MOS晶体管形成在由第二元件隔离区域包围的区域中，并且包括第二栅极绝缘膜和第二栅极电极。 第一元件隔离区域和第二元件隔离区域的上部从半导体基板突出并且它们的拐角是弯曲的。 从第一元件隔离区域接触第一栅极绝缘膜的位置到第一元件隔离区域的顶面端部的宽度等于从第二元件隔离区域接触第二栅极绝缘膜到第二栅极绝缘膜的位置的宽度 第二元件隔离区域的顶表面端。

公开(公告)号：US20090016108A1

公开(公告)日：2009-01-15

申请号：US12106953

申请日：2008-04-21

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.

摘要翻译： 一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据 在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

公开(公告)号：US07298006B2

公开(公告)日：2007-11-20

申请号：US11535514

申请日：2006-09-27

申请人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma ,  Riichiro Shirota ,  Akira Shimizu

发明人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma ,  Riichiro Shirota ,  Akira Shimizu

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.

摘要翻译： 通过栅极绝缘膜在半导体衬底上形成浮栅。 扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。 第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

公开(公告)号：US20070138575A1

公开(公告)日：2007-06-21

申请号：US11565843

申请日：2006-12-01

申请人： Fumitaka Arai ,  Makoto Sakuma

发明人： Fumitaka Arai ,  Makoto Sakuma

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.

摘要翻译： 在存储单元阵列中布置有具有存储单元的多个单元单元和选择栅晶体管以选择存储单元。 第一选择栅极线包括选择栅极晶体管的控制栅极。 在第一选择栅极线之上形成第二选择栅极线。 第一选择栅极线具有依次叠加的第一栅电极，第一栅间绝缘膜和第二栅电极。 第一栅极间绝缘膜具有第一开口部，第一栅极电极和第二栅极电极相互接触。 接触材料形成在第一选择栅极线上，并且使第一选择栅极线和第二选择栅极线彼此电连接。 接触材料配置在不配置第一开口部的第一选择栅极线上。

公开(公告)号：US07122866B2

公开(公告)日：2006-10-17

申请号：US11061824

申请日：2005-02-18

申请人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma

发明人： Fumitaka Arai ,  Yasuhiko Matsunaga ,  Makoto Sakuma

IPC分类号： H01L29/94

CPC分类号： G11C16/0433 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a second element isolating region and includes a second gate insulating film and a second gate electrode. The upper part of the first and second element isolating regions project from a semiconductor substrate and their corners are curved. The width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region is equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.