公开(公告)号：US20090209733A1

公开(公告)日：2009-08-20

申请号：US12293541

申请日：2007-03-20

申请人： Akira Otsuka ,  Makoto Sakuma

发明人： Akira Otsuka ,  Makoto Sakuma

IPC分类号： C07K16/28

CPC分类号： C07K16/2863 ,  A61K2039/505

摘要： A therapeutic agent for rheumatoid arthritis, particularly a therapeutic agent for ameliorating an inflammatory symptom or bone deformity in rheumatoid arthritis, which comprises an antibody that binds to a hepatocyte growth factor receptor as an active ingredient.

摘要翻译： 用于类风湿性关节炎的治疗剂，特别是用于改善类风湿性关节炎的炎性症状或骨畸形的治疗剂，其包含结合肝细胞生长因子受体作为有效成分的抗体。

公开(公告)号：US08133867B2

公开(公告)日：2012-03-13

申请号：US12293541

申请日：2007-03-20

申请人： Akira Otsuka ,  Makoto Sakuma

发明人： Akira Otsuka ,  Makoto Sakuma

IPC分类号： A61K38/00 ,  A61K38/22 ,  C07K16/00

CPC分类号： C07K16/2863 ,  A61K2039/505

摘要： A therapeutic agent for rheumatoid arthritis, particularly a therapeutic agent for ameliorating an inflammatory symptom or bone deformity in rheumatoid arthritis, which comprises an antibody that binds to a hepatocyte growth factor receptor as an active ingredient.

摘要翻译： 用于类风湿性关节炎的治疗剂，特别是用于改善类风湿性关节炎的炎性症状或骨畸形的治疗剂，其包含结合肝细胞生长因子受体作为有效成分的抗体。

公开(公告)号：US07528046B2

公开(公告)日：2009-05-05

申请号：US11676814

申请日：2007-02-20

申请人： Masayuki Ichige ,  Makoto Sakuma ,  Fumitaka Arai

发明人： Masayuki Ichige ,  Makoto Sakuma ,  Fumitaka Arai

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/0638

摘要： A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second guard ring and including second pattern, the method including exposing the resist film by multiple exposure including first and second exposures for forming latent images corresponding to the first and second patterns, a boundary area of the multiple exposure being set on the isolation region, on the first or second guard ring, or on an area between the first guard ring and the memory cell region, forming a resist pattern by developing the resist film, and etching the substrate with the resist pattern as a mask.

摘要翻译： 一种半导体器件的制造方法，包括：衬底，包括第一图案的存储单元区域，存储单元周围的第一保护环，第一保护环周围的第二保护环，第一和第二保护环之间的隔离区域， 电路区域，并且包括第二图案，所述方法包括通过多次曝光曝光所述抗蚀剂膜，所述多次曝光包括用于形成对应于所述第一和第二图案的潜像的第一和第二曝光，所述多次曝光的边界区域设置在 在第一或第二保护环上或第一保护环和存储单元区域之间的区域上，通过显影抗蚀剂膜形成抗蚀剂图案，并用抗蚀剂图案作为掩模蚀刻基板。

公开(公告)号：US20080251881A1

公开(公告)日：2008-10-16

申请号：US12143597

申请日：2008-06-20

申请人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

发明人： Makoto Sakuma ,  Yasuhiko Matsunaga ,  Fumitaka Arai ,  Kikuko Sugimae

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

摘要翻译： 一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。 该装置还包括上接触孔，下接触孔和接触塞。 上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。 底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。 下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。 下接触孔的上部具有与沟槽相同的宽度。 接触塞设置在上接触孔和下接触孔中。

公开(公告)号：US07393747B2

公开(公告)日：2008-07-01

申请号：US11337001

申请日：2006-01-23

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.

摘要翻译： 非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。 控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

公开(公告)号：US07382649B2

公开(公告)日：2008-06-03

申请号：US11148336

申请日：2005-06-09

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Makoto Sakuma ,  Tadashi Iguchi ,  Hisashi Watanobe ,  Hiroaki Tsunoda

IPC分类号： G11C11/34

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.

摘要翻译： 非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第 相邻的存储单元单元阵列在行方向上排列。

公开(公告)号：US20080084728A1

公开(公告)日：2008-04-10

申请号：US11851078

申请日：2007-09-06

申请人： Makoto Sakuma ,  Takuya Futatsuyama

发明人： Makoto Sakuma ,  Takuya Futatsuyama

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L27/0207 ,  H01L27/105

摘要： A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

摘要翻译： 半导体器件包括存储单元阵列区域，存储单元阵列区域的外围的外围电路区域和存储单元阵列区域与外围电路区域之间具有特定宽度的边界区域，存储单元阵列区域包括 包括非易失性半导体存储单元的单元区域，从单元区域的内部延伸到单元区域外的线性布线，以及比边界区域中的线性布线更下层的布线，并且电连接到线性布线， 并且下层布线的布线宽度大于线性布线的宽度，外围电路区域包括经由下层布线电连接到线性布线的图案，不能设置线性布线的边界区域和布线 与线性配线相同。

公开(公告)号：US20080083947A1

公开(公告)日：2008-04-10

申请号：US11868130

申请日：2007-10-05

申请人： Makoto Sakuma

发明人： Makoto Sakuma

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/76802 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328

摘要： A semiconductor device includes a first barrier insulating film formed on upper surfaces of impurity diffusion regions and sidewalls of gate electrodes, a first insulating film formed on the first barrier insulating film so as to bury each region between the gate electrodes, a second barrier insulating film formed continuously on a metal silicide layer and the first insulating film and having an opening with a first width between the gate electrodes adjacent to each other, a second insulating film formed on the second barrier insulating film, and a contact formed by burying a conductor in a contact hole formed so as to pass through the opening of the second barrier insulating film and extend through the second insulating, the first insulating, the first barrier insulating and the gate insulating films, reaching the impurity diffusion region, the contact hole having a second width smaller than the first width.

摘要翻译： 半导体器件包括形成在杂质扩散区域和栅电极的侧壁的上表面上的第一阻挡绝缘膜，形成在第一阻挡绝缘膜上的第一绝缘膜，以便在栅电极之间埋设每个区域;第二阻挡绝缘膜 在金属硅化物层和第一绝缘膜上连续形成，并且在彼此相邻的栅电极之间具有第一宽度的开口，形成在第二阻挡绝缘膜上的第二绝缘膜，以及通过将导体埋入 接触孔形成为穿过第二阻挡绝缘膜的开口并且延伸穿过第二绝缘体，第一绝缘层，第一势垒绝缘膜和栅极绝缘膜，到达杂质扩散区域，接触孔具有第二绝缘膜 宽度小于第一宽度。

公开(公告)号：US07335938B2

公开(公告)日：2008-02-26

申请号：US10971161

申请日：2004-10-25

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： H01L29/72

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.

摘要翻译： 非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准 沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及 电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

公开(公告)号：US07149116B2

公开(公告)日：2006-12-12

申请号：US11337653

申请日：2006-01-24

申请人： Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

发明人： Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

IPC分类号： G11C11/34

CPC分类号： G11C16/10

摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.