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公开(公告)号：US08351277B2
公开(公告)日：2013-01-08
申请号：US13039557
申请日：2011-03-03
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/16 , G11C16/3445 , H01L27/11582
摘要： According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential.
摘要翻译： 根据一个实施例，公开了一种用于操作半导体存储器件的方法。 半导体存储器件包括衬底，层叠体，存储膜，通道体，选择晶体管和布线。 该方法可以通过向布线，选择栅极和字电极层施加第一擦除电位来提高通道体的电位。 此外，在通道体的电位升高之后，在布线和选择栅极保持第一擦除电位的情况下，该方法可以将字电极层的电位降低到低于第一擦除电位的第二擦除电位 。
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公开(公告)号：US20110063914A1
公开(公告)日：2011-03-17
申请号：US12725742
申请日：2010-03-17
CPC分类号： G11C16/0466 , G11C5/02 , G11C16/0483 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.
摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：交替堆叠的包括电极膜和电极间绝缘膜的多层结构; 穿透多层结构的半导体柱; 绝缘膜和设置在电极膜和半导体柱之间的存储层; 以及连接到半导体柱的布线。 在擦除操作中，控制单元执行以下操作：在第一时段期间将布线设置为第一电位的第一操作和低于第一电位的第二电位的电极膜; 以及在第一操作之后的第二周期期间将布线设置在第三电位的第二操作和电极膜处于低于第三电位的第四电位。 第二周期的长度比第一周期短，和/或第三和第四电位之间的差小于第一和第二电位之间的差。
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公开(公告)号：US08194467B2
公开(公告)日：2012-06-05
申请号：US12725742
申请日：2010-03-17
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/0466 , G11C5/02 , G11C16/0483 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.
摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：交替堆叠的包括电极膜和电极间绝缘膜的多层结构; 穿透多层结构的半导体柱; 绝缘膜和设置在电极膜和半导体柱之间的存储层; 以及连接到半导体柱的布线。 在擦除操作中，控制单元执行以下操作：在第一时段期间将布线设置为第一电位的第一操作和低于第一电位的第二电位的电极膜; 以及在第一操作之后的第二周期期间将布线设置在第三电位的第二操作和电极膜处于低于第三电位的第四电位。 第二周期的长度比第一周期短，和/或第三和第四电位之间的差小于第一和第二电位之间的差。
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公开(公告)号：US20110216604A1
公开(公告)日：2011-09-08
申请号：US13039557
申请日：2011-03-03
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/16 , G11C16/3445 , H01L27/11582
摘要： According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential.
摘要翻译： 根据一个实施例，公开了一种用于操作半导体存储器件的方法。 半导体存储器件包括衬底，层叠体，存储膜，通道体，选择晶体管和布线。 该方法可以通过向布线，选择栅极和字电极层施加第一擦除电位来提高通道体的电位。 此外，在通道体的电位升高之后，在布线和选择栅极保持第一擦除电位的情况下，该方法可以将字电极层的电位降低到低于第一擦除电位的第二擦除电位 。
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公开(公告)号：US20100327340A1
公开(公告)日：2010-12-30
申请号：US12821551
申请日：2010-06-23
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括层叠结构单元，半导体柱，存储层，内绝缘膜，外绝缘膜和帽绝缘膜。 该单元包括在多个电极间绝缘膜上沿第一方向交替堆叠的多个电极膜。 支柱沿第一方向刺穿层叠的结构单元。 存储层设置在电极膜和半导体柱之间。 内部绝缘膜设置在存储层和半导体柱之间。 外绝缘膜设置在存储层和电极膜之间。 帽绝缘膜设置在外绝缘膜和电极膜之间，并且帽绝缘膜具有比外绝缘膜更高的相对介电常数。
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公开(公告)号：US06555870B1
公开(公告)日：2003-04-29
申请号：US09605895
申请日：2000-06-29
申请人： Ryouhei Kirisawa
发明人： Ryouhei Kirisawa
IPC分类号： H01L29792
CPC分类号： H01L29/7926 , G11C16/0491 , H01L27/115 , H01L27/11553 , H01L27/11556 , H01L29/7886 , H01L29/792
摘要： A groove 11 is formed in a semiconductor substrate 10. A source region 12 is formed on the bottom of the groove 11 on the side of the surface of the semiconductor substrate 10. A drain region 14 is formed in a portion, in which the groove 11 is not formed, on the side of the surface of the semiconductor substrate 10. Floating gates 30 are formed on both inner side wall portions of the groove 11 as charge storage layers. By thus three-dimensionally forming a memory transistor, it is possible to achieve the high density integration of a nonvolatile semiconductor memory device.
摘要翻译： 沟槽11形成在半导体衬底10中。源极区12形成在半导体衬底10的表面侧上的沟槽11的底部。漏区14形成在凹槽11的一部分中， 11不形成在半导体基板10的表面侧上。浮动栅极30形成在槽11的两个内侧壁部分上，作为电荷存储层。 通过这样三维形成存储晶体管，可以实现非易失性半导体存储器件的高密度集成。
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47.发明授权Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平
公开(公告)号：US5321699A
公开(公告)日：1994-06-14
申请号：US851286
申请日：1992-03-12
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.
摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。
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48.发明授权公开(公告)号：US08581326B2
公开(公告)日：2013-11-12
申请号：US12727644
申请日：2010-03-19
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.
摘要翻译： 一种非易失性半导体存储器件，包括：第一层叠体，其具有第一存储单元的多个第一栅电极;第二层叠体，每个第二层叠体具有第二存储单元的多个第二栅电极，位于第一存储单元的侧表面的栅绝缘膜部; 第二层叠体，各自位于第一和第二层叠体之间的第一半导体层，连接到第一存储单元中的最上面的第一选择晶体管，连接到第二存储单元中最上面的第一选择晶体管，隔离绝缘膜 将第一和第二选择晶体管分离成第一和第二层叠体侧的部分，以及位于从前表面侧到背面侧穿透隔离绝缘膜并连接到第一半导体层的衬底电位施加电极。
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49.再颁专利Electrically erasable programmable read-only memory with NAND cell structure 失效具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：USRE35838E
公开(公告)日：1998-07-07
申请号：US430271
申请日：1995-04-28
申请人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
CPC分类号： G11C16/16
摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.
摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。 存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。 每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。 这些半导体层形成在形成于基板的表面区域的P型阱层中。 阱层用作表面击穿防止层。 在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。 在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。 当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极 的存储单元和阱层。 因此，只能选择所选单元格。
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公开(公告)号：US5597748A
公开(公告)日：1997-01-28
申请号：US247589
申请日：1994-05-23
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。
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