公开(公告)号：US20070298594A1

公开(公告)日：2007-12-27

申请号：US11806926

申请日：2007-06-05

申请人： Ichiro Mizushima ,  Kiyotaka Miyano ,  Katsuaki Natori ,  Yoshio Ozawa

发明人： Ichiro Mizushima ,  Kiyotaka Miyano ,  Katsuaki Natori ,  Yoshio Ozawa

IPC分类号： H01L21/36

CPC分类号： H01L27/11521 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/78

摘要： A semiconductor device fabrication method includes forming an insulating film having an opening on the major surface of single-crystal silicon, and forming an amorphous silicon film on the surface of the single-crystal silicon exposed in the opening and on the surface of the insulating film. The semiconductor device fabrication method further includes performing annealing to change the amorphous silicon film into a single crystal, and forming a single-crystal silicon film, SiGe film, or carbon-containing silicon film by vapor phase growth on a region where the amorphous silicon film is changed into a single crystal.

摘要翻译： 一种半导体器件制造方法，包括在单晶硅的主表面上形成具有开口的绝缘膜，并在暴露于开口部和绝缘膜表面的单晶硅的表面上形成非晶硅膜 。 半导体器件制造方法还包括执行退火以将非晶硅膜改变为单晶，并且通过气相生长在非晶硅膜的区域上形成单晶硅膜，SiGe膜或含碳硅膜 改为单晶。

公开(公告)号：US20080054341A1

公开(公告)日：2008-03-06

申请号：US11892282

申请日：2007-08-21

申请人： Katsuaki Natori ,  Masayuki Tanaka ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Masayuki Tanaka ,  Akihito Yamamoto

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.

摘要翻译： 半导体存储器件包括多个存储晶体管。 每个存储晶体管具有：浮栅电极; 电极间绝缘膜; 和控制栅电极。 浮栅电极在沿着位线方向的截面中包括第一导电膜，跨越第一导电膜的彼此相对的第一侧壁绝缘膜和设置在第一侧壁绝缘膜上的第二导电膜和 第一导电膜。 电极间绝缘膜设置在第二导电膜上。 控制栅电极包括设置在电极间绝缘膜上的第三导电膜和设置在第三导电膜上的第四导电膜。

公开(公告)号：US07803682B2

公开(公告)日：2010-09-28

申请号：US11892282

申请日：2007-08-21

申请人： Katsuaki Natori ,  Masayuki Tanaka ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Masayuki Tanaka ,  Akihito Yamamoto

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.

摘要翻译： 半导体存储器件包括多个存储晶体管。 每个存储晶体管具有：浮栅电极; 电极间绝缘膜; 和控制栅电极。 浮栅电极在沿着位线方向的截面中包括第一导电膜，跨越第一导电膜的彼此相对的第一侧壁绝缘膜和设置在第一侧壁绝缘膜上的第二导电膜和 第一导电膜。 电极间绝缘膜设置在第二导电膜上。 控制栅电极包括设置在电极间绝缘膜上的第三导电膜和设置在第三导电膜上的第四导电膜。

公开(公告)号：US20060273320A1

公开(公告)日：2006-12-07

申请号：US11443275

申请日：2006-05-31

申请人： Katsuaki Natori ,  Masayuki Tanaka

发明人： Katsuaki Natori ,  Masayuki Tanaka

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  C23C16/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31616 ,  H01L27/115 ,  H01L27/11521

摘要： According to an aspect of the invention, there is provided a method of manufacturing a semiconductor device including simultaneously supplying a source gas of an oxide insulating film and H2 to a semiconductor substrate when the oxide insulating film is formed on the semiconductor substrate by a CVD method.

摘要翻译： 根据本发明的一个方面，提供一种制造半导体器件的方法，该半导体器件包括在形成氧化物绝缘膜时同时向半导体衬底提供氧化物绝缘膜和H 2 O 3的源气体 通过CVD法在半导体衬底上。

公开(公告)号：US20070272966A1

公开(公告)日：2007-11-29

申请号：US11802292

申请日：2007-05-22

申请人： Daisuke Nishida ,  Katsuaki Natori ,  Akihito Yamamoto ,  Masayuki Tanaka

发明人： Daisuke Nishida ,  Katsuaki Natori ,  Akihito Yamamoto ,  Masayuki Tanaka

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/513

摘要： A method of fabricating a nonvolatile semiconductor memory device includes forming a first dielectric layer on a major surface of a semiconductor substrate, forming a floating gate electrode layer on the first dielectric layer, and forming a second dielectric layer, which includes a metal oxide film or a stacked film thereof, on the floating gate electrode layer. The method of fabricating the nonvolatile semiconductor memory device further includes forming a control gate electrode layer on the second dielectric layer by using a material including silicon having no silicon (Si)-hydrogen (H) bond.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在半导体衬底的主表面上形成第一电介质层，在第一电介质层上形成浮栅电极层，形成第二电介质层，其包括金属氧化物膜或 在浮栅电极层上形成叠层膜。 制造非易失性半导体存储器件的方法还包括通过使用包含不含硅（Si） - 氢（H）键的硅的材料在第二介电层上形成控制栅电极层。

公开(公告)号：US08741161B2

公开(公告)日：2014-06-03

申请号：US13428535

申请日：2012-03-23

申请人： Yasuyuki Sonoda ,  Kyoichi Suguro ,  Masatoshi Yoshikawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno

发明人： Yasuyuki Sonoda ,  Kyoichi Suguro ,  Masatoshi Yoshikawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L27/228 ,  H01L43/12

摘要： According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.

摘要翻译： 根据一个实施方案，一种制造半导体器件的方法，该方法包括在基底层上形成柱，在基底层上形成绝缘层以通过GCIB法覆盖柱，其中上表面的最下部分 绝缘层低于柱的上表面，并且通过使用CMP方法研磨绝缘层和柱以露出柱的头部，其中抛光的终点是上表面的最下部 绝缘层。

公开(公告)号：US08604573B2

公开(公告)日：2013-12-10

申请号：US13425345

申请日：2012-03-20

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/222 ,  H01L43/08

摘要： According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.

摘要翻译： 根据一个实施例，半导体存储器件包括多个磁阻元件。 在半导体存储器件中，每个磁阻元件包括：形成在半导体衬底上的第一磁性层，第一磁性层具有垂直于其膜表面的易磁化磁化轴; 形成在所述第一磁性层上的非磁性层; 形成在所述非磁性层上的第二磁性层，所述第二磁性层具有与其膜表面垂直的容易的磁化轴; 以及侧壁膜，其被设置成覆盖每个所述磁阻元件的侧壁，并且所述侧壁膜之间具有保护膜，所述侧壁膜沿易磁化轴向所述磁阻元件提供拉伸应力。

公开(公告)号：US20130001716A1

公开(公告)日：2013-01-03

申请号：US13425309

申请日：2012-03-20

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Tadashi Kai

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Tadashi Kai

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.

摘要翻译： 根据实施例，磁阻元件包括下电极，下电极上的第一磁性层，第一磁性层上的第一扩散防止层，第一金属层上的第一界面磁性层，第一金属层上的非磁性层 第一界面磁性层，非磁性层上的第二界面磁性层，第二界面磁性层上的第二扩散防止层，第二扩散防止层上的第二磁性层和第二磁性层上的上部电极层。 第二界面磁性层中的晶体取向部分与另一部分的比例高于第一界面磁性层中晶体取向部分与其它部分的比例。

公开(公告)号：US20120326252A1

公开(公告)日：2012-12-27

申请号：US13425345

申请日：2012-03-20

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

IPC分类号： H01L29/82

CPC分类号： H01L27/222 ,  H01L43/08

摘要： According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.

摘要翻译： 根据一个实施例，半导体存储器件包括多个磁阻元件。 在半导体存储器件中，每个磁阻元件包括：形成在半导体衬底上的第一磁性层，第一磁性层具有垂直于其膜表面的易磁化磁化轴; 形成在所述第一磁性层上的非磁性层; 形成在所述非磁性层上的第二磁性层，所述第二磁性层具有与其膜表面垂直的容易的磁化轴; 以及侧壁膜，其被设置成覆盖每个所述磁阻元件的侧壁，并且所述侧壁膜之间具有保护膜，所述侧壁膜沿易磁化轴向所述磁阻元件提供拉伸应力。

公开(公告)号：US07259094B2

公开(公告)日：2007-08-21

申请号：US11110933

申请日：2005-04-21

申请人： Katsuaki Natori ,  Keisuke Nakazawa ,  Koji Yamakawa ,  Hiroyuki Kanaya ,  Yoshinori Kumura ,  Hiroshi Itokawa ,  Osamu Arisumi

发明人： Katsuaki Natori ,  Keisuke Nakazawa ,  Koji Yamakawa ,  Hiroyuki Kanaya ,  Yoshinori Kumura ,  Hiroshi Itokawa ,  Osamu Arisumi

IPC分类号： H01L21/44 ,  C23C16/00

CPC分类号： H01L27/11502 ,  C23C14/08 ,  C23C14/5806 ,  H01L21/67115 ,  H01L27/11507 ,  H01L28/65

摘要： An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.

摘要翻译： 公开了一种用于制造半导体器件的装置，其包括容纳待处理基板的室，该基板具有含有至少一种将成为挥发性金属化合物的成分的金属元素的膜，加热基板 保持在所述室中的吸附剂和设置在所述室中并通过加热所述基板吸附由所述膜产生的挥发性金属化合物的吸附剂。