公开(公告)号：US20250039097A1

公开(公告)日：2025-01-30

申请号：US18226587

申请日：2023-07-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Amit Kazimirsky ,  Eran Gil Beracha ,  Liron Mula ,  Aviv Kfir ,  Barak Gafni

IPC: H04L47/129 ,  H04L47/30

Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a plurality of ports to facilitate communication over a network. The system also includes a controller to selectively activate or deactivate ports of the system based on queue depths and additional information to improve power efficiency of the system.

公开(公告)号：US12177322B2

公开(公告)日：2024-12-24

申请号：US18314834

申请日：2023-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Liron Mula ,  Barak Gafni

IPC: G06F15/173 ,  H04L69/22 ,  H04L69/323 ,  H04L69/324

Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

公开(公告)号：US20240152438A1

公开(公告)日：2024-05-09

申请号：US17981508

申请日：2022-11-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

公开(公告)号：US20230412519A1

公开(公告)日：2023-12-21

申请号：US17844362

申请日：2022-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Aviv Kfir ,  Miri Shtaif ,  Eran Gil Beracha

IPC: H04L47/56 ,  H04L43/0852 ,  H04L47/625

CPC classification number: H04L47/56 ,  H04L43/0852 ,  H04L47/625

Abstract: A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.

公开(公告)号：US20230224262A1

公开(公告)日：2023-07-13

申请号：US17648260

申请日：2022-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ioannis (Giannis) Patronas ,  Michael Gandelman ,  Liron Mula ,  Aviad Levy ,  Lion Levi ,  Jose Yallouz ,  Paraskevas Bakopoulos ,  Elad Mentovich

IPC: H04L49/00 ,  H04L49/101

CPC classification number: H04L49/3027 ,  H04L49/101 ,  H04L49/3018

Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

公开(公告)号：US20230216837A1

公开(公告)日：2023-07-06

申请号：US17568582

申请日：2022-01-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Barak Gafni ,  Liron Mula

IPC: H04L9/40

CPC classification number: H04L63/0485 ,  H04L63/164 ,  H04L63/162

Abstract: Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device includes multiple ports, a network processing element, a programmable path-selection circuit, and a security IC. The programmable path-selection circuit is configured to operate in a first mode in which first outgoing packets are routed to the security integrated circuit to be encrypted before sending on one of the ports, and first incoming packets, received on one of the ports, are routed to the security integrated circuit to be decrypted. The programmable path-selection circuit is configured to operate in a second mode in which second incoming packets are routed to the security integrated circuit to be encrypted before processing by the network processing element and route second outgoing packets to the security integrated circuit to be decrypted after processing by the network processing element.

公开(公告)号：US11622028B2

公开(公告)日：2023-04-04

申请号：US17198292

申请日：2021-03-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Shpigelman ,  Idan Burstein ,  Aviv Kfir ,  Liron Mula ,  Niv Aibester ,  Gil Levy

IPC: H04L47/33 ,  H04L69/22 ,  H04L47/12 ,  H04L1/00

Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive via one of the ports a packet that originated from a source node and is destined to a destination node, the packet including a mark that is indicative of a cumulative state derived from at least bandwidth utilization conditions of output ports that were traversed by the packet along a path, from the source node up to the network element, to select a port for forwarding the packet toward the destination node, to update the mark of the packet based at least on a value of the mark in the received packet and on a local bandwidth utilization condition of the selected port, and to transmit the packet having the updated mark to the destination node via the selected port.

公开(公告)号：US20220368639A1

公开(公告)日：2022-11-17

申请号：US17869821

申请日：2022-07-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L47/20

Abstract: Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information. Related apparatus and methods are also provided.

公开(公告)号：US20220350713A1

公开(公告)日：2022-11-03

申请号：US17244539

申请日：2021-04-29

Applicant: Mellanox Technologies LTD.

Inventor： Liron Mula ,  Gil Levy ,  Itamar Rabenstein

IPC: G06F11/20 ,  G06F13/20 ,  G06F9/50

Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.

公开(公告)号：US20220239766A1

公开(公告)日：2022-07-28

申请号：US17160407

申请日：2021-01-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Liron Mula ,  Aviv Kfir ,  Amir Mizrahi ,  Niv Aibester

IPC: H04L29/06 ,  H04L12/861 ,  H04L12/931

Abstract: A parsing apparatus includes an interface, a first parser, a second parser and a controller. The interface is configured to receive packets belonging to a plurality of predefined packet types. The first parser is configured to identify any of the packet types. The second parser is configured to identify only a partial subset of the packet types. The controller is configured to receive a packet via the interface, to attempt identifying a packet type of the received packet using the second parser, and in response to detecting that identifying the packet type using the second parser fails, to revert to identify the packet type of the received packet using the first parser.