Abstract:
Various aspect of a system for a linearized transmitter including a power amplifier may include at least one transconductance amplifier that enables generation of a single analog quadrature signal. Transmitter mixers may enable generation of a plurality of upconverted RF signals in a corresponding plurality of RF processing chains based on the generated single analog quadrature signal. In various embodiments of the invention, a gain stage, for example gain stage, may also be referred to as an RF processing chain. Power amplifier circuit may enable generation of a corresponding plurality of RF output signals within a wireless communication system based on the generated plurality of upconverted RF signals.
Abstract:
Methods and systems for a transmitter LOFT cancellation scheme that maintains IQ balance are disclosed. Aspects of one method may include providing current compensation to both differential inputs of a mixer for each of I and Q channels. An initial current compensation of X units may be provided, followed by subsequent compensation as needed. The initial compensation may be provided to each differential input of the mixers used for I and Q channels. The subsequent current compensation for the I channel may be independent of the subsequent current compensation for the Q channel. Subsequent current compensation to a first differential input for a mixer may be increased by Y units while decreasing current compensation to the second differential input of the mixer by Y units. In this manner, the DC common mode level for the mixer may remain the same at the initial DC compensation current of X units for both mixers.
Abstract:
Aspects of a method and system for wide range amplitude detection are provided. In this regard, many electronic systems may require amplitude detection of a variety of signals with widely varying amplitudes. Aspects of the invention may comprise suitable logic, circuitry, and/or code to perform amplitude detection and may be easily configured to accommodate a wide range of amplitudes. In this regard, the configuration of the amplitude detector may be performed via simple design changes and/or may be dynamically configured by suitable logic, circuitry, and/or code. Accordingly, multiplexing a single instance of the wide range amplitude detector and/or multiplexing multiple instances of the wide range amplitude detector may result in reduced design time, reduced circuit size, and/or reduced cost.
Abstract:
The invention enables a compromise between DC offset rejection and image rejection through the use of a bandpass filter having a variable center frequency.
Abstract:
A transmitter includes a dual mode modulator and an amplifier coupled to the dual mode modulator. The dual mode modulator implements a linear modulation scheme during a first mode of the modulator to produce a variable envelope modulated signal. The dual mode modulator implements a non-linear modulation scheme during a second mode of the modulator to produce a constant envelope modulated signal. The amplifier is biased as a linear amplifier during the first mode of the modulator and is biased as a non-linear amplifier during the second mode of the modulator. A feed-forward connection between the dual mode modulator and the amplifier is used to indicate a change in modulation mode and to adjust the bias of the amplifier. A power of the constant envelope modulated signal is increased such that an operating point of the amplifier remains substantially constant during the first and second modes of the modulator.
Abstract:
Methods and systems for digitally controlling transmitter gain compensation are disclosed. Aspects of one method may include applying an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes that may be due to temperature changes. The effective negative resistance may be provided via a plurality of load circuits coupled in parallel to the differential outputs. The plurality of load circuits may have similar effective negative resistances, or the plurality of load circuits may be binary weighted. Each load circuit may be selected via digital control signals that may enable the load circuit. This may allow adjusting of the effective negative resistance by selecting different load circuits.
Abstract:
A circuit may be provided. The circuit may be a component of a dual mode transmitter such as a transmitter from the 802.11x family. The circuit may comprise an amplifier configured to provide amplification of a signal for transmission in either a first transmission mode or a second transmission mode, using power supplied from a power supply, the amplifier including at least one cascode transistor in series with at least one amplifying transistor. The circuit may further comprise a power controller configured to define an operating characteristic of the at least one cascode transistor, and thereby designate an amount of the power from the power supply that is used by the amplifier during the amplification, based on whether the amplifier is to be operated in the first transmission mode or the second transmission mode.
Abstract:
A circuit includes at least two transistors arranged to form a current mirror, at least two transistors operatively coupled to the current mirror, where the transistors are arranged to form a differential pair amplifier, and a follower transistor operatively coupled to the current mirror and to the differential pair. The transistors of the differential pair, the current mirror, and the follower transistor are operatively coupled such that during operation an amplitude of a signal output from the follower transistor is proportional to an amplitude of an signal input into the differential pair.
Abstract:
A dual power mode transmitter is provided to save power when the transmitter switches from normal operating mode to low power operating mode. The dual power mode transmitter achieves power savings by controlling the amount of current draw in the input stage. Alternatively, the transmitter saves power by regulating the voltage at the output node of the input stage.