摘要:
Various aspect of a system for a linearized transmitter including a power amplifier may include at least one transconductance amplifier that enables generation of a single analog quadrature signal. Transmitter mixers may enable generation of a plurality of upconverted RF signals in a corresponding plurality of RF processing chains based on the generated single analog quadrature signal. In various embodiments of the invention, a gain stage, for example gain stage, may also be referred to as an RF processing chain. Power amplifier circuit may enable generation of a corresponding plurality of RF output signals within a wireless communication system based on the generated plurality of upconverted RF signals.
摘要:
A method and system for wireless communication is provided and may include generating a single analog quadrature signal in a chip including RF transmitters and receivers using a baseband processor, and generating output RF signals based on the quadrature signal in corresponding RF transmitters. The output RF signals may be communicated to the RF receivers via a feedback path including circuitry external to the RF receivers. The dedicated circuitry may include a transmit/receive switch and/or an on-chip or off-chip balun. The quadrature signal may include in-phase and quadrature-phase components. The output RF signal communicated via the feedback path may be down-converted utilizing mixers in the RF receivers and communicated to the baseband processor. Distortion in the quadrature signal may be estimated utilizing the communicated down-converted output RF signals and subsequently generated quadrature signals may be predistorted based on the distortion estimation.
摘要:
Various aspect of a system for a linearized transmitter including a power amplifier may include at least one transconductance amplifier that enables generation of a single analog quadrature signal. Transmitter mixers may enable generation of a plurality of upconverted RF signals in a corresponding plurality of RF processing chains based on the generated single analog quadrature signal. In various embodiments of the invention, a gain stage, for example gain stage, may also be referred to as an RF processing chain. Power amplifier circuit may enable generation of a corresponding plurality of RF output signals within a wireless communication system based on the generated plurality of upconverted RF signals.
摘要:
A method and system for wireless communication is provided and may include generating a single analog quadrature signal in a chip including RF transmitters and receivers using a baseband processor, and generating output RF signals based on the quadrature signal in corresponding RF transmitters. The output RF signals may be communicated to the RF receivers via a feedback path including circuitry external to the RF receivers. The dedicated circuitry may include a transmit/receive switch and/or an on-chip or off-chip balun. The quadrature signal may include in-phase and quadrature-phase components. The output RF signal communicated via the feedback path may be down-converted utilizing mixers in the RF receivers and communicated to the baseband processor. Distortion in the quadrature signal may be estimated utilizing the communicated down-converted output RF signals and subsequently generated quadrature signals may be predistorted based on the distortion estimation.
摘要:
Aspects of a method and system for a shared high-power transmit path for a multi-protocol transceiver are disclosed. Aspects of one method may include sharing a first power amplifier with a WLAN signal and a Bluetooth signal. The first power amplifier may amplify the WLAN signal and/or the Bluetooth signal simultaneously, or individually. A second power amplifier may be used to amplify the Bluetooth signal, where the first power amplifier may have a higher gain than the second power amplifier. Power may be reduced to the second power amplifier in instances where the first power amplifier is used to amplify the Bluetooth signal. The Bluetooth signal may be communicated to the first power amplifier via a switching circuit, which may comprise one or more switching stages.
摘要:
Methods and systems for a transmitter LOFT cancellation scheme that maintains IQ balance are disclosed. Aspects of one method may include providing current compensation to both differential inputs of a mixer for each of I and Q channels. An initial current compensation of X units may be provided, followed by subsequent compensation as needed. The initial compensation may be provided to each differential input of the mixers used for I and Q channels. The subsequent current compensation for the I channel may be independent of the subsequent current compensation for the Q channel. Subsequent current compensation to a first differential input for a mixer may be increased by Y units while decreasing current compensation to the second differential input of the mixer by Y units. In this manner, the DC common mode level for the mixer may remain the same at the initial DC compensation current of X units for both mixers.
摘要:
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
摘要:
A semiconductor capacitor that includes a plurality of overlapping conductive layers and a field-effect transistor. The plurality of conductive layers include a first and second conductive layers that are spaced apart to creating a capacitance between the plurality of layers. In the semiconductor capacitor, the FET has a source, a drain and a gate. When the FET is in conduction mode, a capacitance is created between the gate and the conductive path in the semiconductor substrate between the source and the drain. The semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first conductive layer and coupling the gate to the second conductive layer.
摘要:
A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.
摘要:
Methods and systems for digitally controlling transmitter gain compensation are disclosed. Aspects of one method may include applying an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes that may be due to temperature changes. The effective negative resistance may be provided via a plurality of load circuits coupled in parallel to the differential outputs. The plurality of load circuits may have similar effective negative resistances, or the plurality of load circuits may be binary weighted. Each load circuit may be selected via digital control signals that may enable the load circuit. This may allow adjusting of the effective negative resistance by selecting different load circuits.