公开(公告)号：US20090085620A1

公开(公告)日：2009-04-02

申请号：US11862312

申请日：2007-09-27

申请人： Michael R. May ,  Raymond L. Vargas

发明人： Michael R. May ,  Raymond L. Vargas

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  G06F1/06

摘要： A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.

摘要翻译： 时钟系统包括锁相环，相位分配器和控制模块。 锁相环（PLL）产生多个相位偏移输出振荡。 相位分离器基于相位分配器控制信号从多个相位偏移输出振荡中的一个或多个产生时钟信号。 控制模块基于时钟信号的期望设置产生相位分配器控制信号。

公开(公告)号：US20070279027A1

公开(公告)日：2007-12-06

申请号：US11446612

申请日：2006-06-05

申请人： Michael R. May ,  Marcus William May

发明人： Michael R. May ,  Marcus William May

IPC分类号： G05F1/00

CPC分类号： H02M1/084

摘要： A system includes a first semiconductor device, a second semiconductor device, and an external crystal oscillator. The first semiconductor device includes a source voltage output and an external pin input. The first semiconductor device includes a direct current-to-direct current (DC-DC) converter circuit that provides the source voltage output. The second semiconductor device includes a source voltage input that is coupled to the source voltage output of the first semiconductor device and includes a clock signal output. The external crystal oscillator is coupled via an input of the second semiconductor device to a first oscillator clock generation circuit.

摘要翻译： 一种系统包括第一半导体器件，第二半导体器件和外部晶体振荡器。 第一半导体器件包括源极电压输出和外部引脚输入。 第一半导体器件包括提供源极电压输出的直流 - 直流（DC-DC）转换器电路。 第二半导体器件包括耦合到第一半导体器件的源极电压输出并包括时钟信号输出的源极电压输入。 外部晶体振荡器经由第二半导体器件的输入耦合到第一振荡器时钟产生电路。

公开(公告)号：US07245247B1

公开(公告)日：2007-07-17

申请号：US11355934

申请日：2006-02-16

申请人： Michael R. May ,  Matthew D. Felder

发明人： Michael R. May ,  Matthew D. Felder

IPC分类号： H03M3/00

CPC分类号： H03M3/496 ,  G11C27/024 ,  H03M3/454

摘要： An analog-to-digital converter (ADC) includes a modulator and a decimation filter. The modulator includes a sampling circuit, integrator, a quantizer, and feedback circuitry. The sampling circuit includes at least one sampling capacitor and a plurality of dump capacitors. A sum of the capacitance of the dump capacitors is substantially equal to a capacitance of the sampling capacitors. Combined sampling/dump capacitors having approximately equal capacitance may be used with the sampling circuit.

摘要翻译： 模数转换器（ADC）包括调制器和抽取滤波器。 调制器包括采样电路，积分器，量化器和反馈电路。 采样电路包括至少一个采样电容器和多个转储电容器。 转储电容器的电容之和基本上等于采样电容器的电容。 采样电路可以使用具有大致相等电容的组合采样/去电容器。

公开(公告)号：US07227478B1

公开(公告)日：2007-06-05

申请号：US11302761

申请日：2005-12-14

申请人： Jon David Hendrix ,  Michael R. May

发明人： Jon David Hendrix ,  Michael R. May

IPC分类号： H03M7/00

CPC分类号： H03H17/0628

摘要： A sample rate converter includes an up-conversion module, a linear interpolator module, and a parameter control module. The up-conversion module is operable to convert a first data rate to a second data rate of a data signal. The linear interpolator module is operable to receive the data signal at the second data rate and to produce therefrom a data signal at a desired rate based on at least one parameter. The parameter control module is operable to produce the at least one parameter based on the desired rate.

摘要翻译： 采样率转换器包括上转换模块，线性内插器模块和参数控制模块。 上变换模块可操作以将第一数据速率转换为数据信号的第二数据速率。 线性内插器模块可操作以基于第二数据速率接收数据信号，并且基于至少一个参数以期望的速率从其产生数据信号。 参数控制模块可操作以基于期望速率产生至少一个参数。

公开(公告)号：US06567027B2

公开(公告)日：2003-05-20

申请号：US09779810

申请日：2001-02-08

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H03M700

CPC分类号： H03H17/0621 ,  H03M3/418 ,  H03M3/462

摘要： A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.

公开(公告)号：US06259746B1

公开(公告)日：2001-07-10

申请号：US09007218

申请日：1998-01-14

申请人： Howard E. Levin ,  Michael R. May ,  Matthew A. Pendleton

发明人： Howard E. Levin ,  Michael R. May ,  Matthew A. Pendleton

IPC分类号： H04L2704

CPC分类号： H04L27/2608

摘要： In the present invention, carriers associated with a discrete multi-tone (DMT) communications system (10) are sorted according to bit allocation capacity. The number of bits needed to attain a specified bit rate are then allocated beginning with the carrier having the greatest bit allocation capacity and proceeding toward the carrier having the least bit allocation capacity until all bits to are allocated. Once allocated, the power to any unused bins is reduced. Different subsets of the carriers between line cards can be specified in order to reduce crosstalk between adjacent lines.

摘要翻译： 在本发明中，根据比特分配容量对与离散多音（DMT）通信系统（10）相关联的载波进行分类。 然后从具有最大位分配容量的载波开始分配达到指定比特率所需的比特数，并且朝向具有最小比特分配容量的载波进行分配，直到所有比特被分配为止。 一旦分配，任何未使用的箱的功率就会降低。 可以指定线路卡之间的载波的不同子集，以减少相邻线路之间的串扰。

公开(公告)号：US5966054A

公开(公告)日：1999-10-12

申请号：US15846

申请日：1998-01-29

申请人： Michael R. May ,  Michael D. Cave ,  Joseph C. Fong

发明人： Michael R. May ,  Michael D. Cave ,  Joseph C. Fong

IPC分类号： H03B5/12 ,  H03B5/04 ,  H03B5/36

CPC分类号： H03B5/366

摘要： A method that includes the steps of producing a digital code (104) based at least in part on an integrated circuit capacitance and adjusting a frequency of the clocking signal in response to the digital code (106). A method that includes the steps of in a first mode of operation, producing a fixed frequency clocking signal, the fixed frequency clocking signal having a frequency tolerance less than 20 units per million and, in a second mode of operation, producing a variable frequency clocking signal, the variable frequency clocking signal having a frequency variability range greater than 200 units per million. An apparatus for providing a clocking signal includes a tuner circuit (12) and an oscillator circuit (16) responsive to the tuner circuit (12). The tuner circuit (12) is responsive to a clock signal source (38), an integrated circuit capacitance, and a reference resistor (18). The tuner circuit (12) produces a digital code signal. (22) The oscillator circuit (16) includes at least one adjustable integrated circuit capacitor (30, 32) responsive to the digital code signal (22) and is capable of producing the clocking signal.

摘要翻译： 一种方法，其包括以下步骤：至少部分地基于集成电路电容产生数字代码（104），并响应于所述数字代码（106）调整所述计时信号的频率。 一种方法，其包括以下步骤：在第一操作模式中产生固定频率时钟信号，所述固定频率时钟信号具有小于每百万个百万个单位的频率容限，并且在第二操作模式中，产生可变频率时钟 信号，可变频率时钟信号的频率变化范围大于200个百万分之一。 用于提供时钟信号的装置包括调谐器电路（12）和响应于调谐器电路（12）的振荡器电路（16）。 调谐器电路（12）响应时钟信号源（38），集成电路电容和参考电阻（18）。 调谐器电路（12）产生数字码信号。 （22）响应于数字码信号（22），振荡器电路（16）包括至少一个可调整的集成电路电容器（30,32），并且能够产生时钟信号。

公开(公告)号：US5835536A

公开(公告)日：1998-11-10

申请号：US383026

申请日：1995-02-02

申请人： Michael R. May ,  Terence L. Johnson ,  Matthew A. Pendleton

发明人： Michael R. May ,  Terence L. Johnson ,  Matthew A. Pendleton

IPC分类号： H04L27/26 ,  H04L27/34 ,  H04K1/10

CPC分类号： H04L27/3411 ,  H04L27/2614 ,  H04L27/2618

摘要： A symbol generator (804) generates a time-domain discrete multi-tone symbol (810). A magnitude comparator (812) compares the magnitude of the time-domain discrete multi-tone symbol (810) with a magnitude threshold. When the magnitude of the time-domain discrete multi-tone symbol (810) compares unfavorably to the magnitude threshold, a magnitude adjusting symbol (816) is added to the time-domain discrete multi-tone symbol (810) such that the magnitude of the time-domain discrete multi-tone symbol (810) is reduced, thereby reducing the peak-to-average requirements (PAR).

摘要翻译： 符号生成器（804）生成时域离散多色调符号（810）。 幅度比较器（812）将时域离散多音调符号（810）的幅度与幅度阈值进行比较。 当时域离散多音调符号（810）的大小与幅度阈值不利地比较时，幅度调整符号（816）被加到时域离散多音调符号（810），使得 降低了时域离散多音调符号（810），从而降低了峰值平均要求（PAR）。

公开(公告)号：US5719856A

公开(公告)日：1998-02-17

申请号：US418048

申请日：1995-04-07

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H04B1/58 ,  H04B1/40

CPC分类号： H04B1/58 ,  H04Q2213/13034 ,  H04Q2213/13199 ,  H04Q2213/13209 ,  H04Q2213/13302 ,  H04Q2213/13306 ,  H04Q2213/1332

摘要： A transmitter/receiver interface (12) for use with a bi-directional transmission path (18) couples a transmitter (14) and a receiver (16) to the bi-directional transmission path (18). The transmitter/receiver interface (12) separates transmitted signals (20) and received signals (22) and routes them from the transmitter (14) and to the receiver (16) with negligible interference. The transmitter/receiver interface (12) incorporates coupling elements (44 and 50) that couple the transmitter to the transmission path and incorporates networks that couple the receiver to the transmission path. Impedances of the networks are derived based on the coupling elements and the transfer characteristics of the transmission path to provide consistent attenuation of the transmit signal over a large frequency range.

摘要翻译： 与双向传输路径（18）一起使用的发射机/接收机接口（12）将发射机（14）和接收机（16）耦合到双向传输路径（18）。 发射机/接收机接口（12）以可忽略的干扰分离发射信号（20）和接收信号（22）并将其从发射机（14）和接收机（16）路由到接收机（16）。 发射机/接收机接口（12）包括耦合元件（44和50），耦合元件将发射机耦合到传输路径并且包括将接收机耦合到传输路径的网络。 网络的阻抗基于传输路径的耦合元件和传输特性导出，以在大的频率范围内提供发射信号的一致的衰减。

公开(公告)号：US09172344B2

公开(公告)日：2015-10-27

申请号：US13070683

申请日：2011-03-24

申请人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

发明人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

IPC分类号： H04B1/06 ,  H04B7/00 ,  H03G3/30 ,  H04B17/318

CPC分类号： H03G3/3073 ,  H03G3/3052 ,  H04B17/318

摘要： A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

摘要翻译： 在接收机中接收射频（RF）信号，并且可以获得基于来自信号的信息的各种计数。 可以在累积窗口期间累积超过第一和第二阈值的RF信号的多个样本的计数。 从这些计数中的第一个可以确定计数是否超过对应于第一预定计数值的第一度量，如果是，则可以减小RF增益元件的增益。 从这些计数中的第二个可以确定该计数是否超过对应于第二预定计数值的第二度量，如果不是，则可以增加增益。