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41.发明申请ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权迭代写暂停技术来改善读取存储器系统的延迟公开(公告)号：US20110026318A1
公开(公告)日：2011-02-03
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。
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42.发明授权公开(公告)号：US08004884B2
公开(公告)日：2011-08-23
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G11C11/00
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。
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公开(公告)号：US20130166821A1
公开(公告)日：2013-06-27
申请号：US13336287
申请日：2011-12-23
IPC分类号： G06F12/02
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F11/1658 , G06F11/1666 , G06F12/02
摘要： Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
摘要翻译： 具有低延迟的持久数据存储通过包括接收包括写入数据的低延迟存储命令的方法来提供。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。
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公开(公告)号：US20130166826A1
公开(公告)日：2013-06-27
申请号：US13619424
申请日：2012-09-14
IPC分类号： G06F12/00
CPC分类号： G06F3/0688 , G06F3/0601 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0652 , G06F12/0246 , G06F2212/7201 , G06F2212/7211
摘要： An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.
摘要翻译： 一个实施例是用于在固态存储板上的固态存储设备上建立第一逻辑地址和第一物理地址之间的对应关系的方法。 固态存储装置包括通过物理地址识别的多个物理存储器位置，并且由位于与固态存储板分离的主板上的软件模块建立。 第一逻辑地址和第一物理地址之间的对应关系存储在固态存储设备上的位于固态存储板上的地址转换器模块可访问的位置。 固态存储器件位于固态存储板上。 基于先前建立的第一逻辑地址和第一物理地址之间的对应关系，地址转换器模块将第一逻辑地址转换为第一物理地址。
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公开(公告)号：US08848471B2
公开(公告)日：2014-09-30
申请号：US13569486
申请日：2012-08-08
申请人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
CPC分类号： G11C29/50 , G11C11/406 , G11C29/023 , G11C29/028 , G11C29/50016
摘要： A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.
摘要翻译： 用于确定优化的刷新速率的方法涉及测试单元行的刷新率，确定行的错误率，评估行的错误率; 并重复这些步骤以减少刷新率，直到错误率大于约束，此时设置较慢的刷新率。
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公开(公告)号：US09772802B2
公开(公告)日：2017-09-26
申请号：US13619424
申请日：2012-09-14
CPC分类号： G06F3/0688 , G06F3/0601 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0652 , G06F12/0246 , G06F2212/7201 , G06F2212/7211
摘要： An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.
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47.发明授权公开(公告)号：US08769374B2
公开(公告)日：2014-07-01
申请号：US12903695
申请日：2010-10-13
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page.
摘要翻译： 包括用于在存储器中接收写入数据和存储器页面的写入地址的方法的非易失性存储器的多写入耐久性和错误控制编码。 写入数据被划分成多个子块，每个子块包括写入数据的q个比特。 响应于子块和纠错码（ECC），在计算机上产生纠错位。 包含错误校正位的至少一个附加子块被附加到分区写入数据，并且产生写入字。 通过对每个子块进行执行来产生写字：选择码字，使得码字对子块进行编码，并且与与存储器页相关联的多个存储单元的当前电荷电平一致; 连接所选择的码字以形成写入字; 并将写入字写入存储器页面。
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公开(公告)号：US08656130B2
公开(公告)日：2014-02-18
申请号：US13336287
申请日：2011-12-23
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F11/1658 , G06F11/1666 , G06F12/02
摘要： Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.
摘要翻译： 通过包括接收包括写入数据的低延迟存储命令的方法来提供持续数据存储。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。
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公开(公告)号：US08621328B2
公开(公告)日：2013-12-31
申请号：US13040482
申请日：2011-03-04
CPC分类号： G11C16/349 , G06F11/1012
摘要： Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into a plurality of regions. The plurality of regions includes a first region and a second region that are implemented by the same memory technology. The memory is subject to degradation as a result of write operations. The write data is classified as dynamic data or static data. The write data is encoded using a first type of encoding in response to the write data being classified as dynamic. The write data encoded using the first type of encoding is stored in the first region of the memory. The write data is encoded using a second type of encoding and stored in the second region of the memory in response to classifying the write data as static data.
摘要翻译： 使用磨损聚焦技术将数据存储在内存中，以提高耐久性。 用于存储数据的方法包括接收要写入到逻辑上划分为多个区域的存储器中的写入数据。 多个区域包括由相同存储器技术实现的第一区域和第二区域。 由于写入操作，存储器会降级。 写数据分为动态数据或静态数据。 响应于写入数据被分类为动态，使用第一类型的编码对写入数据进行编码。 使用第一类型的编码编码的写入数据被存储在存储器的第一区域中。 响应于将写入数据分类为静态数据，写入数据使用第二类型的编码进行编码并存储在存储器的第二区域中。
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公开(公告)号：US08560922B2
公开(公告)日：2013-10-15
申请号：US13040531
申请日：2011-03-04
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1048 , G11C11/5628 , G11C11/5642 , G11C13/00 , G11C16/00 , G11C29/42 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.
摘要翻译： 用于闪存的坏块管理，包括用于存储数据的方法。 该方法包括接收包括写数据的写请求。 识别用于存储写入数据的存储器块。 存储器块包括多个页面。 确定存储器块的误码率（BER），并响应于超过BER阈值的BER从写入数据产生扩展写入数据。 扩展的写入数据的特征在于低于BER阈值的预期BER。 扩展的写入数据使用纠错码（ECC）进行编码。 编码的扩展写入数据被写入存储器块。
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