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    LOW LATENCY AND PERSISTENT DATA STORAGE
    1.
    发明申请
    LOW LATENCY AND PERSISTENT DATA STORAGE 有权
    低期和持续数据存储

    公开(公告)号：US20130166821A1

    公开(公告)日：2013-06-27

    申请号：US13336287

    申请日：2011-12-23

    申请人： Blake G. Fitch ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Todd E. Takken

    发明人： Blake G. Fitch ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Todd E. Takken

    IPC分类号： G06F12/02

    CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1658 ,  G06F11/1666 ,  G06F12/02

    摘要： Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

    摘要翻译： 具有低延迟的持久数据存储通过包括接收包括写入数据的低延迟存储命令的方法来提供。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。

    Low latency and persistent data storage
    2.
    发明授权
    Low latency and persistent data storage 有权
    低延迟和持久数据存储

    公开(公告)号：US08656130B2

    公开(公告)日：2014-02-18

    申请号：US13336287

    申请日：2011-12-23

    申请人： Blake G. Fitch ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Todd E. Takken

    发明人： Blake G. Fitch ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Todd E. Takken

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1658 ,  G06F11/1666 ,  G06F12/02

    摘要： Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

    摘要翻译： 通过包括接收包括写入数据的低延迟存储命令的方法来提供持续数据存储。 写入数据被写入由以第一访问速度为特征的非易失性固态存储器技术实现的第一存储器件。 确认写入数据已成功写入第一个存储器件。 写入数据被写入由易失性存储器技术实现的第二存储器件。 当在第一存储装置中累积了预定量的数据时，第一存储装置中的数据的至少一部分被写入第三存储装置。 第三存储器件通过非易失性固态存储器技术来实现，其特征在于比第一存取速度慢的第二存取速度。

    Internet telephony unit and software for enabling internet telephone access from traditional telephone interface
    4.
    发明授权
    Internet telephony unit and software for enabling internet telephone access from traditional telephone interface 有权
    互联网电话单元和用于通过传统电话接口实现互联网电话接入的软件

    公开(公告)号：US09112953B2

    公开(公告)日：2015-08-18

    申请号：US13605614

    申请日：2012-09-06

    申请人： Todd E. Takken

    发明人： Todd E. Takken

    IPC分类号： H04L12/66 ,  H04M7/00 ,  H04L29/06 ,  H04M15/00 ,  H04L29/08

    CPC分类号： H04M7/0057 ,  H04L29/06 ,  H04L67/14 ,  H04L67/303 ,  H04L69/24 ,  H04L69/329 ,  H04M15/00 ,  H04M15/49 ,  H04M15/55 ,  H04M15/56 ,  H04M15/8044 ,  H04M2215/202 ,  H04M2215/2046 ,  H04M2215/42 ,  H04M2215/46 ,  H04M2215/745

    摘要： Automatic selection and establishment of a communications connection between a telephone device to a receiver device, including entering an address of a receiver device into the telephone device for initiating the communications connection to the receiver device, and automatically selecting a communications network for establishing the communications connection to the receiver device, and selecting the communications network from an internet-based network, a hybrid telephone/internet network, and a telephone network. Automatically determine network access capabilities of the receiver device based on the address of the receiver device, and automatically evaluate the cost of establishing a communications connection for each of the communications networks which the receiver device is capable of accessing. The communications network with the lowest cost is selected.

    摘要翻译： 自动选择和建立电话设备到接收机设备之间的通信连接，包括将接收机设备的地址输入到电话设备中，用于发起到接收机设备的通信连接，以及自动选择用于建立通信连接的通信网络 并且从基于因特网的网络，混合电话/互联网和电话网络选择通信网络。 基于接收机设备的地址自动确定接收机设备的网络接入能力，并自动评估为接收机设备能够访问的每个通信网络建立通信连接的成本。 选择成本最低的通信网络。

    Massively parallel supercomputer
    5.
    发明授权
    Massively parallel supercomputer 有权
    大容量并行超级计算机

    公开(公告)号：US08667049B2

    公开(公告)日：2014-03-04

    申请号：US13566024

    申请日：2012-08-03

    申请人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampap ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

    发明人： Matthias A. Blumrich ,  Dong Chen ,  George L. Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampap ,  Philip Heidlberger ,  Gerard V. Kopcsay ,  Lawrence S. Mok ,  Todd E. Takken

    IPC分类号： G06F15/173

    CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

    摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

    摘要翻译： 数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。 在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却​​要求的最佳平衡。 单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。 片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。 多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

    Collective network for computer structures
    7.
    发明授权
    Collective network for computer structures 有权
    计算机结构集体网络

    公开(公告)号：US08001280B2

    公开(公告)日：2011-08-16

    申请号：US11572372

    申请日：2005-07-18

    申请人： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

    发明人： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

    IPC分类号： G06F15/16

    CPC分类号： G06F15/17381 ,  H04L1/1845 ,  H04L12/4641

    摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices ate included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

    摘要翻译： 一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。 全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。 路由器设备包括通过链路互连网络的节点，以便于在虚拟网络和类结构的节点处执行低延迟全局处理操作。 全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。 当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。