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41.发明申请公开(公告)号：US20120144272A1
公开(公告)日：2012-06-07
申请号：US12960004
申请日：2010-12-03
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译： 在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。 该系统包括与存储器通信的解码器。 解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。 该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。 响应于接收到包含码字的页面之前写入的数据和存储器中的其他页面的内容，生成第二层校验符号。 响应于第二层校验符号校正码字。 校正的码字被输出。
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42.发明授权公开(公告)号：US08004884B2
公开(公告)日：2011-08-23
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G11C11/00
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。
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公开(公告)号：US08861266B2
公开(公告)日：2014-10-14
申请号：US13619473
申请日：2012-09-14
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.
摘要翻译： 一种用于操作相变存储器的方法，包括初始化存储单元，所述存储单元包括：具有大于其宽度的长度的第一导电电极和与所述长度对准的轴线; 第二导电电极，其具有与第一导电电极的轴成一定角度的边缘; 绝缘体，其在所述第一导电电极的端部和所述第二导电电极的边缘之间提供间隔距离; 以及覆盖所述第一导电电极的主要部分和所述第二导电电极的至少一部分的相变材料。 初始化存储单元包括在相变材料中形成第一非晶态材料区域。 在第一无定形材料区域内形成活性结晶材料区域。 通过在活性结晶材料区域内产生第二非晶态材料区域将信息存储在存储器单元中。
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公开(公告)号：US08575008B2
公开(公告)日：2013-11-05
申请号：US12873058
申请日：2010-08-31
IPC分类号： H01L21/00
CPC分类号： H01L45/126 , H01L45/04 , H01L45/1226 , H01L45/144
摘要： Creating a localized region of material having a target chemical composition by defining an electrical circuit on a substrate, and depositing on the electrical circuit one or more layers of materials having one or more chemical compositions. An electrical current pulse is applied to the electrical circuit to create a self-aligned localized region having the target chemical composition. Applying the electrical current pulse causes a portion of the one or more layers of materials to be heated, resulting in the target chemical composition.
摘要翻译： 通过在基板上限定电路来形成具有目标化学成分的材料的局部区域，以及在电路上沉积具有一种或多种化学成分的一层或多层材料。 电流脉冲施加到电路以产生具有目标化学成分的自对准局部区域。 施加电流脉冲导致一层或多层材料的一部分被加热，导致目标化学成分。
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公开(公告)号：US08144508B2
公开(公告)日：2012-03-27
申请号：US12984682
申请日：2011-01-05
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C2013/0052
摘要： Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.
摘要翻译： 读取相变存储器的技术，减轻电阻漂移。 一种预期的方法包括将多个电输入信号应用于存储器单元。 该方法包括从多个电输入信号测量来自存储器单元的多个电输出信号。 该方法包括根据存储单元中非晶材料的配置来计算多个电输出信号的不变分量。 该方法还包括基于不变分量来确定存储器单元的存储器状态。 在本发明的一个实施例中，该方法还包括将多个电输出信号映射到多个测量区域的测量区域。 测量区域对应于存储器单元的存储器状态。
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公开(公告)号：US20110317481A1
公开(公告)日：2011-12-29
申请号：US12823924
申请日：2010-06-25
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.
摘要翻译： 具有并联电路径的平面相变存储单元。 存储单元包括具有大于其宽度的长度的第一导电电极区域和与该长度对准的轴线。 存储单元还包括具有与第一导电电极区域的轴成一定角度的边缘的第二导电电极区域。 存储单元还包括绝缘体区域，其在第一导电电极区域的端部和第二导电电极区域的边缘之间提供横向间隔距离，绝缘体区域包括绝缘膜的至少一部分，并且横向间隔距离是响应的 到绝缘膜的厚度。
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公开(公告)号：US20130016556A1
公开(公告)日：2013-01-17
申请号：US13619473
申请日：2012-09-14
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.
摘要翻译： 一种用于操作相变存储器的方法，包括初始化存储单元，所述存储单元包括：具有大于其宽度的长度的第一导电电极和与所述长度对准的轴线; 第二导电电极，其具有与第一导电电极的轴成一定角度的边缘; 绝缘体，其在所述第一导电电极的端部和所述第二导电电极的边缘之间提供间隔距离; 以及覆盖所述第一导电电极的主要部分和所述第二导电电极的至少一部分的相变材料。 初始化存储单元包括在相变材料中形成第一非晶态材料区域。 在第一无定形材料区域内形成活性结晶材料区域。 通过在活性结晶材料区域内产生第二非晶态材料区域将信息存储在存储器单元中。
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公开(公告)号：US08685785B2
公开(公告)日：2014-04-01
申请号：US13619493
申请日：2012-09-14
IPC分类号： H01L21/02
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.
摘要翻译： 一种在衬底上制造相变存储单元的方法。 该方法包括：蚀刻衬底中的第一沟槽; 在第一沟槽中沉积第一导体层; 在所述第一沟槽中的所述第一导体层上沉积第一绝缘体层; 以与第一沟槽成一定角度蚀刻衬底中的第二沟槽; 在所述第二沟槽中沉积第二绝缘体层; 在所述第二沟槽中的所述第二绝缘体层上沉积第二导体层; 并沉积相变材料。 沉积的相变材料与第一导体层和第二导体层接触。
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公开(公告)号：US08624217B2
公开(公告)日：2014-01-07
申请号：US12823924
申请日：2010-06-25
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.
摘要翻译： 具有并联电路径的平面相变存储单元。 存储单元包括具有大于其宽度的长度的第一导电电极区域和与该长度对准的轴线。 存储单元还包括具有与第一导电电极区域的轴成一定角度的边缘的第二导电电极区域。 存储单元还包括绝缘体区域，其在第一导电电极区域的端部和第二导电电极区域的边缘之间提供横向间隔距离，绝缘体区域包括绝缘膜的至少一部分，并且横向间隔距离是响应的 到绝缘膜的厚度。
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公开(公告)号：US07929338B2
公开(公告)日：2011-04-19
申请号：US12392032
申请日：2009-02-24
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C2013/0052
摘要： Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.
摘要翻译： 读取相变存储器的技术，减轻电阻漂移。 一种预期的方法包括将多个电输入信号应用于存储器单元。 该方法包括从多个电输入信号测量来自存储器单元的多个电输出信号。 该方法包括根据存储单元中非晶材料的配置来计算多个电输出信号的不变分量。 该方法还包括基于不变分量来确定存储器单元的存储器状态。 在本发明的一个实施例中，该方法还包括将多个电输出信号映射到多个测量区域的测量区域。 测量区域对应于存储器单元的存储器状态。
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