公开(公告)号：US20210066135A1

公开(公告)日：2021-03-04

申请号：US16558928

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L29/08 ,  H01L23/528 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11507

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US20210013305A1

公开(公告)日：2021-01-14

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US10825484B2

公开(公告)日：2020-11-03

申请号：US16702926

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Si-Woo Lee

IPC: G11C5/10 ,  H01L27/108 ,  G11C11/401

Abstract: A method of forming an integrated assembly includes providing a construction having laterally-spaced digit-line-contact-regions and having intervening regions between the laterally-spaced digit-line-contact-regions; forming an expanse of non-conductive-semiconductor-material which extends across the digit-line-contact-regions and the intervening regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions; forming openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions; forming conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; and forming metal-containing-digit-lines over the non-conductive-semiconductor-material.

公开(公告)号：US20200287003A1

公开(公告)日：2020-09-10

申请号：US16294759

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L29/16 ,  H01L29/207 ,  H01L29/08 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20200286906A1

公开(公告)日：2020-09-10

申请号：US16810009

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10734388B1

公开(公告)日：2020-08-04

申请号：US16248534

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US09754889B2

公开(公告)日：2017-09-05

申请号：US14975746

申请日：2015-12-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/5283 ,  H01L28/00 ,  H01L29/41766 ,  H01L29/4236

Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US09449978B2

公开(公告)日：2016-09-20

申请号：US14148402

申请日：2014-01-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Mingtao Li ,  Haitao Liu ,  Deepak Chandra Pandey ,  Mark Fischer

IPC: H01L27/108 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10879 ,  H01L27/1052 ,  H01L27/10891 ,  H01L29/66613 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7857

Abstract: A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.

Abstract translation: 一种半导体器件包括凹入的存取器件，其包括第一柱，第二柱，连接第一和第二柱的沟道区，以及设置在沟道区上的栅。 沟道区具有比第一柱和第二柱的宽度窄的宽度。 凹陷进入装置的阵列包括从基板突出的多个支柱和多个通道区域。 每个通道区域具有小于约10nm的宽度并且连接相邻的柱以形成多个无连接的凹入式接入设备。 一种形成至少一个凹陷进入装置的方法还包括在衬底上形成柱，形成至少与柱相连的沟道区，沟道区具有相对较窄的宽度，以及形成至少部分围绕沟道区的栅极 至少三面。

公开(公告)号：US20160126354A1

公开(公告)日：2016-05-05

申请号：US14992966

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20150364377A1

公开(公告)日：2015-12-17

申请号：US14836257

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.