公开(公告)号：US06879193B2

公开(公告)日：2005-04-12

申请号：US10484904

申请日：2002-11-20

申请人： Minoru Okamoto ,  Shinichi Marui ,  Kazuhiro Okabayashi

发明人： Minoru Okamoto ,  Shinichi Marui ,  Kazuhiro Okabayashi

IPC分类号： G06F1/24 ,  H03K17/22 ,  H03L7/00

CPC分类号： G06F1/24

摘要： In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

摘要翻译： 在作为断电对象的电路块110中，电压检测电路130和134分别设置在电源端子140和142附近，并且电压检测电路132和136设置在远离端子140的给定位置处， 142分别在两个电源系统的电源线141和143上。 电压检测电路仅由MOS晶体管构成。 在再次接通电源电路150的电源时，在所有电压检测电路检测到电源电压达到预定电位之后，复位信号产生电路160停止向电路块110输入复位信号 因此，由于在电源电压到达预定电压之后停止复位状态，因此半导体集成电路被正常初始化。 这提供了能够适当地产生上电复位信号的半导体集成电路。

公开(公告)号：US06842852B1

公开(公告)日：2005-01-11

申请号：US09500086

申请日：2000-02-08

申请人： Masayuki Yamasaki ,  Minoru Okamoto

发明人： Masayuki Yamasaki ,  Minoru Okamoto

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30061 ,  G06F9/30072

摘要： An execution control instruction is applied to an information processor of the type processing instructions by pipelining to suppress the occurrence of branch hazard. The execution control instruction contains: a condition field for specifying an execution condition; and an instruction-specifying field for defining, in binary code, the number of instructions to be executed only conditionally. In response to the execution control instruction, a nullification controller decides, based on control flags provided from an arithmetic logic unit, whether or not the execution condition specified by the condition field is satisfied. And based on the outcome of this decision, the controller determines whether or not that number of instructions, which has been defined by the instruction-specifying field for instructions succeeding the execution control instruction, should be nullified. If the controller has determined that the specified number of succeeding instructions should be nullified since the execution condition is not met, then the controller asserts a nullification signal to be supplied to the arithmetic logic unit. In this manner, a large number of succeeding instructions are executable conditionally using an execution control instruction of a short word length.

摘要翻译： 通过流水线将执行控制指令应用于类型处理指令的信息处理器，以抑制分支危险的发生。 执行控制指令包含：用于指定执行条件的条件字段; 以及指令指定字段，用于以二进制代码定义仅有条件地执行的指令的数量。 响应于执行控制指令，无效控制器基于从算术逻辑单元提供的控制标志来确定是否满足由条件字段指定的执行条件。 并且，根据该决定的结果，控制器判定是否将由执行控制指令之后的指令指定指定字段定义的指令数量无效。 如果由于执行条件不满足控制器已经确定指定数量的后续指令将被取消，则控制器断言要提供给算术逻辑单元的无效信号。 以这种方式，大量的后续指令可以使用短字长度的执行控制指令有条件地执行。

公开(公告)号：US6125153A

公开(公告)日：2000-09-26

申请号：US997378

申请日：1997-12-23

申请人： Yuji Sugisawa ,  Minoru Okamoto

发明人： Yuji Sugisawa ,  Minoru Okamoto

IPC分类号： H03M13/41 ,  H03D1/00

CPC分类号： H03M13/6569 ,  H03M13/4107

摘要： In a data processor for updating path metrics in Viterbi decoding, an ACS processing can be efficiently executed with small power consumption. An ACS processing unit obtains an updated path metric through an ACS processing on the basis of pre-update path metrics read from a memory. In the memory, two pre-update path metrics necessary for obtaining one updated path metric are stored in an even address and an odd address having common bits excluding the least significant bits, so that the two pre-update path metrics can be read through one access. In the first cycle, the ACS processing unit makes an access to the memory and obtains a first updated path metric through the ACS processing on the basis of the thus read two pre-update path metrics. In the second cycle, without making any access to the memory, the ACS processing unit obtains a second updated path metric through the ACS processing on the basis of the two pre-update path metrics read in the first cycle.

摘要翻译： 在用于更新维特比解码中的路径度量的数据处理器中，可以以小的功耗有效地执行ACS处理。 ACS处理单元基于从存储器读取的更新前路径度量，通过ACS处理获得更新的路径度量。 在存储器中，用于获得一个更新的路径度量所需的两个预更新路径量度被存储在偶数地址和具有不包括最低有效位的公共位的奇数地址中，使得两个预更新路径量度可以通过一个 访问。 在第一周期中，ACS处理单元访问存储器，并且基于这样读取的两个预更新路径度量，通过ACS处理获得第一更新路径度量。 在第二周期中，ACS处理单元在不对存储器进行任何访问的情况下，基于在第一周期读取的两个预更新路径量度通过ACS处理获得第二更新路径量度。

公开(公告)号：US5715470A

公开(公告)日：1998-02-03

申请号：US126563

申请日：1993-09-27

申请人： Nobuo Asano ,  Mitsuru Uesugi ,  Toshihiro Ishikawa ,  Minoru Okamoto

发明人： Nobuo Asano ,  Mitsuru Uesugi ,  Toshihiro Ishikawa ,  Minoru Okamoto

IPC分类号： G06F17/10 ,  H03M13/41 ,  G06F7/00 ,  G06F15/00

CPC分类号： H03M13/6502 ,  G06F17/10 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/413 ,  H03M13/4169 ,  H03M13/6505

摘要： An arithmetic apparatus in which while data read out of a memory is shifted by means of a barrel shifter by a shift bit number designated by data standing for an output signal of an inverter, data standing for an output signal of the barrel shifter is inputted to a shift register to thereby perform Viterbi decoding at a high speed.

摘要翻译： 一种算术装置，其中当通过桶形移位器通过由反相器的输出信号指定的数据指定的移位位数来移位存储器的数据时，将桶形移位器的输出信号的数据输入到 移位寄存器，从而以高速执行维特比解码。