公开(公告)号：US06751773B2

公开(公告)日：2004-06-15

申请号：US09833061

申请日：2001-04-12

申请人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Masayuki Yamasaki

发明人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Masayuki Yamasaki

IPC分类号： H03M1303

CPC分类号： H03M13/23

摘要： A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.

摘要翻译： 编码装置包括移位寄存器，输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位，并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位， 输入一位输入比特序列，输入比特关联的多项式项中的系数中的高阶一个。 接下来，逻辑运算部分导出乘积的异或逻辑和，然后输出和作为代码序列的位。

公开(公告)号：US06754870B2

公开(公告)日：2004-06-22

申请号：US09833787

申请日：2001-04-13

申请人： Takao Yoshida ,  Minoru Okamoto ,  Masayuki Yamasaki ,  Kazuhiro Okabayashi

发明人： Takao Yoshida ,  Minoru Okamoto ,  Masayuki Yamasaki ,  Kazuhiro Okabayashi

IPC分类号： H03M1300

CPC分类号： H03M13/091 ,  G06F9/3879 ,  H03M13/6516 ,  H03M13/6569

摘要： To enable high-speed CRC operation and flexible use of various generating polynomials without causing significant increase in circuit scale, the CRC operation unit uses circuits generally provided for a DSP and some additional circuits. The CRC operation unit includes: a generating polynomial supply section having a first general register for storing an arbitrary generating polynomial and a selector for selectively outputting the generating polynomial or data of which all bits has a value of 0; an operation data supply section having a memory, a shift register, a second general register, and a barrel shifter, for outputting operation data for CRC operation based on transmitting/receiving data; an operation section for performing CRC operation using the generating polynomial output from the generating polynomial supply section and the operation data output from the operation data supply section; and an operation instruction execution control section for controlling the operations of the above sections.

摘要翻译： 为了实现高速CRC操作和灵活使用各种生成多项式而不引起电路规模的显着增加，CRC操作单元使用通常为DSP提供的电路和一些附加电路。 CRC操作单元包括：生成多项式提供部分，具有用于存储任意生成多项式的第一通用寄存器和用于选择性地输出所有位具有值0的生成多项式或数据的选择器; 具有存储器，移位寄存器，第二通用寄存器和桶形移位器的操作数据提供部分，用于基于发送/接收数据输出用于CRC操作的操作数据; 操作部分，用于使用从生成多项式提供部分输出的生成多项式和从操作数据提供部分输出的操作数据来执行CRC操作; 以及操作指令执行控制部分，用于控制上述部分的操作。

公开(公告)号：US06842852B1

公开(公告)日：2005-01-11

申请号：US09500086

申请日：2000-02-08

申请人： Masayuki Yamasaki ,  Minoru Okamoto

发明人： Masayuki Yamasaki ,  Minoru Okamoto

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30061 ,  G06F9/30072

摘要： An execution control instruction is applied to an information processor of the type processing instructions by pipelining to suppress the occurrence of branch hazard. The execution control instruction contains: a condition field for specifying an execution condition; and an instruction-specifying field for defining, in binary code, the number of instructions to be executed only conditionally. In response to the execution control instruction, a nullification controller decides, based on control flags provided from an arithmetic logic unit, whether or not the execution condition specified by the condition field is satisfied. And based on the outcome of this decision, the controller determines whether or not that number of instructions, which has been defined by the instruction-specifying field for instructions succeeding the execution control instruction, should be nullified. If the controller has determined that the specified number of succeeding instructions should be nullified since the execution condition is not met, then the controller asserts a nullification signal to be supplied to the arithmetic logic unit. In this manner, a large number of succeeding instructions are executable conditionally using an execution control instruction of a short word length.

摘要翻译： 通过流水线将执行控制指令应用于类型处理指令的信息处理器，以抑制分支危险的发生。 执行控制指令包含：用于指定执行条件的条件字段; 以及指令指定字段，用于以二进制代码定义仅有条件地执行的指令的数量。 响应于执行控制指令，无效控制器基于从算术逻辑单元提供的控制标志来确定是否满足由条件字段指定的执行条件。 并且，根据该决定的结果，控制器判定是否将由执行控制指令之后的指令指定指定字段定义的指令数量无效。 如果由于执行条件不满足控制器已经确定指定数量的后续指令将被取消，则控制器断言要提供给算术逻辑单元的无效信号。 以这种方式，大量的后续指令可以使用短字长度的执行控制指令有条件地执行。

公开(公告)号：US20050163233A1

公开(公告)日：2005-07-28

申请号：US11022811

申请日：2004-12-28

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

IPC分类号： G06F11/10 ,  H03M13/23 ,  H03M13/41 ,  H04L1/00 ,  H04B14/04

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.

摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理数据的位长度等于2n位长。

公开(公告)号：US06477661B2

公开(公告)日：2002-11-05

申请号：US09974807

申请日：2001-10-12

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

IPC分类号： G06F1100

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.

摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。

公开(公告)号：US06289429B1

公开(公告)日：2001-09-11

申请号：US08812711

申请日：1997-03-06

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： G06F1200

摘要： A memory device including a first memory and a second memory. A first processor generates a first address for defining a location to be accessed in the first memory and a second address for defining a location to be accessed in the second memory. A second processor generates a third address. A memory control section controls access to the first memory and access to the second memory. The memory control section includes an address conversion section for converting the third address so as to represent either one of the first address and the second address.

公开(公告)号：US08603339B2

公开(公告)日：2013-12-10

申请号：US12675600

申请日：2008-08-26

申请人： Katsuhiko Maeda ,  Minoru Okamoto

发明人： Katsuhiko Maeda ,  Minoru Okamoto

IPC分类号： C02F3/00

CPC分类号： C02F3/342 ,  C02F3/006 ,  C02F3/341 ,  C02F3/348 ,  C02F2103/20 ,  C02F2103/22 ,  C02F2103/26 ,  C02F2103/32 ,  C02F2209/36 ,  C02F2303/06

摘要： Excess sludge production in a bioreactor of a wastewater treatment plant in which excess sludge is being produced is reduced by adding an activated sludge material having a chitinase specific activity of at least 150 Units/g-MLSS and a pectinase specific activity of at least 120 Units/g-MLSS to the bioreactor. After the addition of the activated sludge material, the bioreactor is controlled by adding the activated sludge material when any one of the chitinase activity, the pectinase activity, and the protease specific of the sludge in the bioreactor drops below the lower limits of 50 Units/L, 40 Units/L, and 0.3 Units/L, respectively.

摘要翻译： 通过添加具有至少150单位/ g-MLSS的几丁质酶比活性和至少120单位的果胶酶特异性活性的活性污泥材料，可以减少生产过剩污泥的废水处理厂的生物反应器中的过剩污泥生产 / g-MLSS到生物反应器。 添加活性污泥材料后，生物反应器中的几丁质酶活性，果胶酶活性和污泥蛋白酶特异性中的任何一种下降到50单位/ L，40单位/ L，0.3单位/ L。

公开(公告)号：US07877238B2

公开(公告)日：2011-01-25

申请号：US10938116

申请日：2004-09-10

申请人： Kiyoaki Watanabe ,  Yohko Kawai ,  Takayuki Mitsuhashi ,  Dai Furuie ,  Minoru Okamoto

发明人： Kiyoaki Watanabe ,  Yohko Kawai ,  Takayuki Mitsuhashi ,  Dai Furuie ,  Minoru Okamoto

IPC分类号： G06F17/10 ,  G06F7/60

CPC分类号： G06K9/6251 ,  G06F19/00 ,  G06N3/02 ,  G16H15/00 ,  G16H50/20

摘要： A data classification supporting method capable of easily discriminating a cell to which unknown data belongs and cells similar to the unknown data from each other is obtained. This classification compares cell vector data of each cell with the unknown data, decides a cell having cell vector data closest to the unknown data and cells having cell vector data secondly to nthly close to the unknown data as a minimum cell and similar cells respectively and displays a minimum cell mark and similar cell marks indicating the minimum cell and the similar cells respectively on a classification map.

摘要翻译： 获得能够容易地识别未知数据所属的单元和彼此类似于未知数据的单元的数据分类支持方法。 该分类将每个小区的小区矢量数据与未知数据进行比较，将具有最接近未知数据的小区矢量数据的小区和具有小区向量数据的小区分别作为最小小区和类似小区分别第二至第n个接近未知数据的小区显示 在分类图上分别指示最小细胞和相似细胞的最小细胞标记和类似细胞标记。

公开(公告)号：US20060119387A1

公开(公告)日：2006-06-08

申请号：US11264138

申请日：2005-11-02

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： H03K19/177

CPC分类号： H03K19/17776 ,  H03K19/1737 ,  H03K19/1776 ,  H03K19/17784

摘要： In a programmable cell included in a first region, configuration information is stored in a volatile memory, while in a programmable cell included in a second region, configuration information is stored in a non-volatile memory. Configuration information for a sub-process common to a plurality of processes is stored in the non-volatile memory.

摘要翻译： 在包括在第一区域中的可编程单元中，配置信息被存储在易失性存储器中，而在包括在第二区域中的可编程单元中，配置信息被存储在非易失性存储器中。 用于多个处理共同的子处理的配置信息存储在非易失性存储器中。

公开(公告)号：US20060095727A1

公开(公告)日：2006-05-04

申请号：US11304818

申请日：2005-12-16

申请人： Minoru Okamoto ,  Katsuhiko Ueda

发明人： Minoru Okamoto ,  Katsuhiko Ueda

IPC分类号： G06F9/40

CPC分类号： G06F9/30196 ,  G06F9/30181

摘要： An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

摘要翻译： 一种用于顺序读取和执行存储在存储装置中的程序的信息处理装置，包括：程序计数器，用于将用于读取程序的地址输出到存储装置; 指令解码器，用于响应于指示在构成程序中的指令的至少一个字段中使用的代码的类型被限制为预定数量或更少的周期的控制信号来解码从存储器装置读取的指令; 以及用于执行与从指令解码器输出的解码结果对应的处理的控制装置。 指令解码器具有可重构电路，用于响应于控制信号改变电路配置，使得基于所使用的代码的类型的码中的码之间的关系进行解码，并且解码结果，该关系被设置 使得字段中比特值的改变次数减少。