公开(公告)号：US06842852B1

公开(公告)日：2005-01-11

申请号：US09500086

申请日：2000-02-08

申请人： Masayuki Yamasaki ,  Minoru Okamoto

发明人： Masayuki Yamasaki ,  Minoru Okamoto

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30061 ,  G06F9/30072

摘要： An execution control instruction is applied to an information processor of the type processing instructions by pipelining to suppress the occurrence of branch hazard. The execution control instruction contains: a condition field for specifying an execution condition; and an instruction-specifying field for defining, in binary code, the number of instructions to be executed only conditionally. In response to the execution control instruction, a nullification controller decides, based on control flags provided from an arithmetic logic unit, whether or not the execution condition specified by the condition field is satisfied. And based on the outcome of this decision, the controller determines whether or not that number of instructions, which has been defined by the instruction-specifying field for instructions succeeding the execution control instruction, should be nullified. If the controller has determined that the specified number of succeeding instructions should be nullified since the execution condition is not met, then the controller asserts a nullification signal to be supplied to the arithmetic logic unit. In this manner, a large number of succeeding instructions are executable conditionally using an execution control instruction of a short word length.

摘要翻译： 通过流水线将执行控制指令应用于类型处理指令的信息处理器，以抑制分支危险的发生。 执行控制指令包含：用于指定执行条件的条件字段; 以及指令指定字段，用于以二进制代码定义仅有条件地执行的指令的数量。 响应于执行控制指令，无效控制器基于从算术逻辑单元提供的控制标志来确定是否满足由条件字段指定的执行条件。 并且，根据该决定的结果，控制器判定是否将由执行控制指令之后的指令指定指定字段定义的指令数量无效。 如果由于执行条件不满足控制器已经确定指定数量的后续指令将被取消，则控制器断言要提供给算术逻辑单元的无效信号。 以这种方式，大量的后续指令可以使用短字长度的执行控制指令有条件地执行。

公开(公告)号：US6125153A

公开(公告)日：2000-09-26

申请号：US997378

申请日：1997-12-23

申请人： Yuji Sugisawa ,  Minoru Okamoto

发明人： Yuji Sugisawa ,  Minoru Okamoto

IPC分类号： H03M13/41 ,  H03D1/00

CPC分类号： H03M13/6569 ,  H03M13/4107

摘要： In a data processor for updating path metrics in Viterbi decoding, an ACS processing can be efficiently executed with small power consumption. An ACS processing unit obtains an updated path metric through an ACS processing on the basis of pre-update path metrics read from a memory. In the memory, two pre-update path metrics necessary for obtaining one updated path metric are stored in an even address and an odd address having common bits excluding the least significant bits, so that the two pre-update path metrics can be read through one access. In the first cycle, the ACS processing unit makes an access to the memory and obtains a first updated path metric through the ACS processing on the basis of the thus read two pre-update path metrics. In the second cycle, without making any access to the memory, the ACS processing unit obtains a second updated path metric through the ACS processing on the basis of the two pre-update path metrics read in the first cycle.

摘要翻译： 在用于更新维特比解码中的路径度量的数据处理器中，可以以小的功耗有效地执行ACS处理。 ACS处理单元基于从存储器读取的更新前路径度量，通过ACS处理获得更新的路径度量。 在存储器中，用于获得一个更新的路径度量所需的两个预更新路径量度被存储在偶数地址和具有不包括最低有效位的公共位的奇数地址中，使得两个预更新路径量度可以通过一个 访问。 在第一周期中，ACS处理单元访问存储器，并且基于这样读取的两个预更新路径度量，通过ACS处理获得第一更新路径度量。 在第二周期中，ACS处理单元在不对存储器进行任何访问的情况下，基于在第一周期读取的两个预更新路径量度通过ACS处理获得第二更新路径量度。

公开(公告)号：US5715470A

公开(公告)日：1998-02-03

申请号：US126563

申请日：1993-09-27

申请人： Nobuo Asano ,  Mitsuru Uesugi ,  Toshihiro Ishikawa ,  Minoru Okamoto

发明人： Nobuo Asano ,  Mitsuru Uesugi ,  Toshihiro Ishikawa ,  Minoru Okamoto

IPC分类号： G06F17/10 ,  H03M13/41 ,  G06F7/00 ,  G06F15/00

CPC分类号： H03M13/6502 ,  G06F17/10 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/413 ,  H03M13/4169 ,  H03M13/6505

摘要： An arithmetic apparatus in which while data read out of a memory is shifted by means of a barrel shifter by a shift bit number designated by data standing for an output signal of an inverter, data standing for an output signal of the barrel shifter is inputted to a shift register to thereby perform Viterbi decoding at a high speed.

摘要翻译： 一种算术装置，其中当通过桶形移位器通过由反相器的输出信号指定的数据指定的移位位数来移位存储器的数据时，将桶形移位器的输出信号的数据输入到 移位寄存器，从而以高速执行维特比解码。

公开(公告)号：US5504927A

公开(公告)日：1996-04-02

申请号：US994106

申请日：1992-12-21

申请人： Minoru Okamoto ,  Mikio Sakakibara

发明人： Minoru Okamoto ,  Mikio Sakakibara

IPC分类号： G06F13/12 ,  G06F13/42 ,  G06F13/00 ,  G06F13/20

CPC分类号： G06F13/423 ,  Y02B60/1228 ,  Y02B60/1235

摘要： The present invention provides a data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit to and receive from an external apparatus serial data and the processor processing data inputted to the data transfer device and transmitting the processed data to the data transfer device to be further transmitted to the external apparatus, the date input/output control device characterized in that a clock of the data input/output control device for an operation thereof is a transfer clock utilized by the external apparatus and the transfer clock is slower than a clock for the processor.The data input/output control device comprises a controller for controlling the data input and the data output of the data transfer device, a flag holding unit for holding a flag which shows if the data have been inputted to the data transfer device by the processor or the external apparatus, a first synchronization circuit for synchronizing an output from the flag holding unit with the transfer clock, the output being sent to the controller, and a second synchronization circuit for synchronizing the output from the flag holding unit with the clock for the processor.

摘要翻译： 本发明提供一种将单片微型计算机与数据传送装置和处理器一体化的数据输入/输出控制装置，所述数据传送装置被构造为向外部装置发送和接收串行数据和输入的处理器处理数据 所述数据输入/输出控制装置的特征在于，用于其操作的数据输入/输出控制装置的时钟为 由外部设备和传输时钟使用的传输时钟比处理器的时钟慢。 数据输入/输出控制装置包括用于控制数据输入和数据传送装置的数据输出的控制器，标记保持单元，用于保持标志，该标志显示数据是否已被处理器输入到数据传送装置;或者 外部设备，用于将来自标志保持单元的输出与传送时钟同步的第一同步电路，输出被发送到控制器，以及第二同步电路，用于使来自标志保持单元的输出与处理器的时钟同步 。