公开(公告)号：US06946719B2

公开(公告)日：2005-09-20

申请号：US10728230

申请日：2003-12-03

申请人： Christopher J. Petti ,  S. Brad Herner

发明人： Christopher J. Petti ,  S. Brad Herner

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L27/10 ,  H01L27/102 ,  H01L29/00

CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with it. In preferred embodiments, the silicide is cobalt silicide, and the antifuse preferably silicon oxide, silicon nitride, or silicon oxynitride grown on the colbalt silicide. The junction diode and contact-antifuse unit can be used as a memory cell, which is advantageously used in a monolithic three dimensional memory array.

摘要翻译： 本发明提供了一种垂直取向的结二极管，其具有与其电极之一接触的接触 - 反熔丝单元。 接触 - 反熔丝单元形成在结二极管上方或下方，并且包括形成在其上并与其接触的介电反熔丝层的硅化物。 在优选的实施方案中，硅化物是硅化钴，反熔丝优选在硅化钴上生长的氧化硅，氮化硅或氮氧化硅。 结二极管和接触 - 反熔丝单元可用作存储单元，其有利地用于单片三维存储器阵列中。

公开(公告)号：US20140030836A1

公开(公告)日：2014-01-30

申请号：US13558843

申请日：2012-07-26

申请人： Venkatesan Murali ,  Steve Babayan ,  Christopher J. Petti

发明人： Venkatesan Murali ,  Steve Babayan ,  Christopher J. Petti

IPC分类号： H01L33/02 ,  H01L21/762

CPC分类号： H01L33/0079 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L33/007

摘要： A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.

摘要翻译： 一种制造电子器件的方法包括提供碳化硅或类金刚石碳供体，并将离子注入施主体的第一表面以限定解理面。 在注入之后，在第一表面上形成外延层，并且临时载体耦合到外延层。 在切割平面处从供体体中切割薄层，并将临时载体从薄片上移除。 在一些实施例中，从层板和外延层制造发光二极管或高电子迁移率晶体管。

公开(公告)号：US08349664B2

公开(公告)日：2013-01-08

申请号：US12855462

申请日：2010-08-12

申请人： Scott Brad Herner ,  Christopher J. Petti ,  Tanmay Kumar

发明人： Scott Brad Herner ,  Christopher J. Petti ,  Tanmay Kumar

IPC分类号： H01L21/82

CPC分类号： H01L27/249 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.

摘要翻译： 在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HfxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。 本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

公开(公告)号：US20120167969A1

公开(公告)日：2012-07-05

申请号：US13020849

申请日：2011-02-04

申请人： Christopher J. Petti

发明人： Christopher J. Petti

IPC分类号： H01L31/02

CPC分类号： H01L27/1421 ,  H01L31/0747 ,  H01L31/1892 ,  Y02E10/50

摘要： A structure to provide a Zener diode to avoid shunt formation is disclosed. An undoped or lightly doped monocrystalline thin semiconductor lamina is cleaved from a donor body which is not permanently affixed to a support element. The lamina may be annealed at high temperature to remove damage from a prior implant. At least one aperture is formed through the lamina, either due to flaws in the cleaving process, or intentionally following cleaving. Heavily doped amorphous silicon layers having opposite conductivity types are deposited on opposite faces of the lamina, one forming the emitter and one a base contact to a photovoltaic cell, while the lamina forms the base of the cell. The heavily doped layers contact in the aperture, forming a Zener diode. This Zener diode prevents formation of shunts, and may behave as a bypass diode if the cell is placed under heavy reverse bias, as when one cell in a series string is shaded while the rest of the string is exposed to sun.

摘要翻译： 公开了提供齐纳二极管以避免分流形成的结构。 未掺杂或轻掺杂的单晶薄半导体层从不永久地固定到支撑元件的施主体断开。 层可以在高温下退火以去除以前的植入物的损伤。 由于切割过程中的缺陷，或者故意在切割之后，至少一个孔通过层形成。 具有相反导电类型的重掺杂非晶硅层沉积在层的相对表面上，一个形成发射极，另一个与光伏电池的基极接触，而薄层形成电池的基极。 重掺杂层在孔中接触，形成齐纳二极管。 该齐纳二极管防止分流器的形成，并且如果电池放置在较强的反向偏压下，则可能表现为旁路二极管，如串联串中的一个电池阴影而串的其余部分暴露在阳光下时。

公开(公告)号：US20110306177A1

公开(公告)日：2011-12-15

申请号：US13215836

申请日：2011-08-23

申请人： Samuel V. Dunton ,  Christopher J. Petti ,  Usha Raghuram

发明人： Samuel V. Dunton ,  Christopher J. Petti ,  Usha Raghuram

IPC分类号： H01L21/82

CPC分类号： H01L27/1021 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/90

摘要： A method is described for reducing dielectric overetch. The method includes: (1) forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, the conductive or semiconductor features including pillars that each include a vertically oriented diode; (2) depositing second dielectric fill directly on the planar surface; and (3) etching a void in the second dielectric fill, wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer. Numerous other aspects are provided.

摘要翻译： 描述了一种减少电介质过蚀刻的方法。 该方法包括：（1）形成共同导电或半导体特征和介电蚀刻停止层的基本平坦的表面，所述导电或半导体特征包括每个包括垂直取向的二极管的柱; （2）将第二电介质填充物直接沉积在平面上; 以及（3）蚀刻所述第二介电填充物中的空隙，其中所述蚀刻在所述第二介电填充物和所述电介质蚀刻停止层之间是选择性的，其中所述蚀刻停止在所述电介质蚀刻停止层上。 提供了许多其他方面。

公开(公告)号：US20110095438A1

公开(公告)日：2011-04-28

申请号：US12911900

申请日：2010-10-26

申请人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

发明人： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

摘要翻译： 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

公开(公告)号：US07928007B2

公开(公告)日：2011-04-19

申请号：US12363588

申请日：2009-01-30

申请人： Christopher J. Petti

发明人： Christopher J. Petti

IPC分类号： H01L21/4763

CPC分类号： H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

摘要翻译： 在本发明的第一优选实施例中，导电特征形成在第一电介质蚀刻停止层上，并且第二电介质材料沉积在导电特征之上和之间。 在第一和第二电介质之间选择性的导电特征的通孔蚀刻将停止在电介质蚀刻停止层上，限制过蚀刻。 在第二实施例中，多个导电特征以消减图案和蚀刻工艺形成，填充有电介质填充物，然后形成为与导电特征和电介质填充物共同构成的表面。 电介质蚀刻停止层沉积在表面上，然后第三电介质覆盖电介质蚀刻停止层。 当通过第三电介质蚀刻接触时，该选择性蚀刻停止在电介质蚀刻停止层上。 第二蚀刻与导电特征接触。

公开(公告)号：US07759666B2

公开(公告)日：2010-07-20

申请号：US11819989

申请日：2007-06-29

申请人： Tanmay Kumar ,  Christopher J. Petti

发明人： Tanmay Kumar ,  Christopher J. Petti

IPC分类号： H01L29/02

CPC分类号： H01L27/24 ,  G11C13/0004

摘要： A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.

摘要翻译： 非易失性存储器件包括半导体二极管操作元件和半导体读/写开关元件。

公开(公告)号：US07554832B2

公开(公告)日：2009-06-30

申请号：US11461339

申请日：2006-07-31

申请人： Luca G. Fasoli ,  Christopher J. Petti ,  Roy E. Scheuerlein

发明人： Luca G. Fasoli ,  Christopher J. Petti ,  Roy E. Scheuerlein

IPC分类号： G11C11/00

CPC分类号： G11C8/14

摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

公开(公告)号：US20090142921A1

公开(公告)日：2009-06-04

申请号：US12363588

申请日：2009-01-30

申请人： Christopher J. Petti

发明人： Christopher J. Petti

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/465 ,  H01L21/463

CPC分类号： H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.

摘要翻译： 在本发明的第一优选实施例中，导电特征形成在第一电介质蚀刻停止层上，并且第二电介质材料沉积在导电特征之上和之间。 在第一和第二电介质之间选择性的导电特征的通孔蚀刻将停止在电介质蚀刻停止层上，限制过蚀刻。 在第二实施例中，多个导电特征以消减图案和蚀刻工艺形成，填充有电介质填充物，然后形成为与导电特征和电介质填充物共同构成的表面。 电介质蚀刻停止层沉积在表面上，然后第三电介质覆盖电介质蚀刻停止层。 当通过第三电介质蚀刻接触时，该选择性蚀刻停止在电介质蚀刻停止层上。 第二蚀刻与导电特征接触。