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1.发明授权Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化公开(公告)号：US08809128B2
公开(公告)日：2014-08-19
申请号：US12911900
申请日：2010-10-26
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译： 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。
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2.发明申请METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 有权用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置公开(公告)号：US20110095438A1
公开(公告)日：2011-04-28
申请号：US12911900
申请日：2010-10-26
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译： 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。
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3.发明授权Methods of forming pillars for memory cells using sequential sidewall patterning 有权使用顺序侧壁图案形成记忆单元柱的方法公开(公告)号：US08741696B2
公开(公告)日：2014-06-03
申请号：US12911944
申请日：2010-10-26
IPC分类号： H01L21/82
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译： 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。
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4.发明申请METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING 有权使用顺序方向图形成存储器细胞的支架的方法公开(公告)号：US20110095338A1
公开(公告)日：2011-04-28
申请号：US12911944
申请日：2010-10-26
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译： 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。
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公开(公告)号：US20090168480A1
公开(公告)日：2009-07-02
申请号：US12005346
申请日：2007-12-27
IPC分类号： G11C5/02 , H01L21/308
CPC分类号： G03F7/2022 , B82Y10/00 , H01L27/0207 , H01L27/1021 , H01L27/112 , H01L27/224 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085
摘要： A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.
摘要翻译： 非易失性存储器件包括以基本上六边形图案布置的多个非易失性存储单元。 非易失性存储单元可以是柱形非易失性存储单元，其可以使用三重或四重曝光光刻或通过使用自组装层进行图案化。
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6.发明申请MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME 审中-公开多种抗体存储细胞及其形成，程序和感觉的方法公开(公告)号：US20090086521A1
公开(公告)日：2009-04-02
申请号：US11864870
申请日：2007-09-28
CPC分类号： G11C17/16 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C17/06 , G11C17/146 , G11C17/165 , G11C2213/32 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states.
摘要翻译： 描述了制造，编程和感测多级一次可编程存储器单元的方法，所述存储单元包括诸如二极管的导向元件和串联的两个，三个或更多个介质反熔丝。 反熔丝可以具有不同的厚度，或者可以由具有不同介电常数的介电材料或两者形成。 选择反熔丝和编程脉冲，使得当单元被编程时，存储单元中的最大电压降仅跨越反熔丝中的一个，而另一个反熔丝允许一些漏电流。 在一些实施例中，具有最大电压降的反熔丝分解，而其它反熔丝保持完整。 以这种方式，可以单独地分解反熔丝，因此具有两个，三个或更多个反熔丝的存储单元可以实现三个，四个或更多个唯一数据状态中的任何一个。
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7.发明授权Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders 有权使用包含可逆极性字线和位线解码器的无源元件存储器阵列的方法公开(公告)号：US07463546B2
公开(公告)日：2008-12-09
申请号：US11461364
申请日：2006-07-31
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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公开(公告)号：US20080025134A1
公开(公告)日：2008-01-31
申请号：US11461372
申请日：2006-07-31
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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9.发明授权Passive element memory array incorporating reversible polarity word line and bit line decoders 有权无源元件存储阵列，包含可逆极性字线和位线解码器公开(公告)号：US07554832B2
公开(公告)日：2009-06-30
申请号：US11461339
申请日：2006-07-31
IPC分类号： G11C11/00
CPC分类号： G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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公开(公告)号：US07499304B2
公开(公告)日：2009-03-03
申请号：US11461419
申请日：2006-07-31
IPC分类号： G11C11/00
CPC分类号： G11C17/16 , G11C17/165
摘要： A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.
摘要翻译： 公开了具有相关制造和编程技术的一次性现场可编程（OTP）存储单元。 根据一个实施例的OTP存储器单元包括与转向元件串联的至少一个电阻变化元件。 使用反向偏置操作来对存储单元进行现场编程，该反向偏压操作可以减少通过阵列的漏电流，以及降低驱动电路在程序运行中通常产生的电压电平。 可以通过在制造过程中将存储器单元从其初始状态切换到第二电阻状态来制造存储器单元阵列。 在一个实施例中，出厂切换操作可以包括弹出每个存储单元的反熔丝以使它们成为第二电阻状态。 将第二电阻状态的存储单元的阵列提供给终端用户。 控制电路还具有存储器阵列，其可以将所选择的单元的电阻切换回其初始电阻状态，以根据从用户或主机设备接收的数据对阵列进行编程。
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