公开(公告)号：US20240087211A1

公开(公告)日：2024-03-14

申请号：US17941578

申请日：2022-09-09

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  John BURGESS ,  Magnus ANDERSSON ,  Timo VIITANEN ,  Levi OLIVER

IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T17/005

Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.

公开(公告)号：US20230237729A1

公开(公告)日：2023-07-27

申请号：US18129334

申请日：2023-03-31

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Tero KARRAS ,  Samuli LAINE ,  William Parsons NEWHALL, JR. ,  Ronald Charles BABICH, JR. ,  John BURGESS ,  Ignacio LLAMAS

IPC: G06T15/06

CPC classification number: G06T15/06

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.

公开(公告)号：US20230041724A1

公开(公告)日：2023-02-09

申请号：US17968485

申请日：2022-10-18

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS ,  Ronald Charles BABICH, JR. ,  William Parsons Newhall, JR.

IPC: G06T15/06 ,  G06T17/10 ,  G06F9/48 ,  G06F9/50

Abstract: Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query.

公开(公告)号：US20220292760A1

公开(公告)日：2022-09-15

申请号：US17829954

申请日：2022-06-01

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06T15/08 ,  G06F9/50 ,  G06F9/30 ,  G06T17/00

Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. For example, traversal efficiency is improved by combining programmable traversals based on ray operations with per-node static configurations that modify traversal behavior. The per-node static configurations enable creators of acceleration data structures to optimize for potential traversals without necessarily requiring detailed information about ray characteristics and ray operations used when traversing the acceleration structure. Moreover, by providing for selective exclusion of certain nodes using per-node static configurations, less memory is needed to express an acceleration structure that includes, for example, different geometric levels of details corresponding to a single object.

公开(公告)号：US20220189099A1

公开(公告)日：2022-06-16

申请号：US17689268

申请日：2022-03-08

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06N3/02 ,  G06T15/00

Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.

公开(公告)号：US20210390757A1

公开(公告)日：2021-12-16

申请号：US16897909

申请日：2020-06-10

Applicant: NVIDIA Corporation

Inventor： Gregory MUTHLER ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00 ,  G06N3/02

Abstract: Ray tracing hardware accelerators supporting multiple specifiers for controlling the traversal of a ray tracing acceleration data structure are disclosed. For example, traversal efficiency and complex ray tracing effects can be achieved by specifying traversals through such data structures using both programmable ray operations and explicit node masking. The explicit node masking utilizes dedicated fields in the ray and in nodes of the acceleration data structure to control traversals. Ray operations, however, are programmable per ray using opcodes and additional parameters to control traversals. Traversal efficiency is improved by enabling more aggressive culling of parts of the data structure based on the combination of explicit node masking and programmable ray operations. More complex ray tracing effects are enabled by providing for dynamic selection of nodes based on individual ray characteristics.

公开(公告)号：US20200302676A1

公开(公告)日：2020-09-24

申请号：US16893107

申请日：2020-06-04

Applicant: NVIDIA CORPORATION

Inventor： Samuli LAINE ,  Timo AILA ,  Tero KARRAS ,  Gregory MUTHLER ,  William P. NEWHALL, JR. ,  Ronald C. BABICH, JR. ,  Craig KOLB ,  Ignacio LLAMAS ,  John BURGESS

IPC: G06T15/06 ,  G06T15/00

Abstract: Methods and systems are described in some examples for changing the traversal of an acceleration data structure in a highly dynamic query-specific manner, with each query specifying test parameters, a test opcode and a mapping of test results to actions. In an example ray tracing implementation, traversal of a bounding volume hierarchy by a ray is performed with the default behavior of the traversal being changed in accordance with results of a test performed using the test opcode and test parameters specified in the ray data structure and another test parameter specified in a node of the bounding volume hierarchy. In an example implementation a traversal coprocessor is configured to perform the traversal of the bounding volume hierarchy.

公开(公告)号：US20200051317A1

公开(公告)日：2020-02-13

申请号：US16101206

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Greg MUTHLER ,  Ronald Charles BABICH, JR. ,  William Parsons NEWHALL, JR. ,  Peter NELSON ,  Jim ROBERTSON ,  John BURGESS

IPC: G06T15/06 ,  G06T17/00 ,  G06N5/04 ,  G06F9/38 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.

公开(公告)号：US20200050451A1

公开(公告)日：2020-02-13

申请号：US16101247

申请日：2018-08-10

Applicant: NVIDIA Corporation

Inventor： Ronald Babich ,  John BURGESS ,  Jack CHOQUETTE ,  Tero KARRAS ,  Samuli LAINE ,  Ignacio LLAMAS ,  Gregory MUTHLER ,  William Parsons NEWHALL, JR.

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60

Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.