公开(公告)号：US07061792B1

公开(公告)日：2006-06-13

申请号：US10215678

申请日：2002-08-10

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/412 ,  G11C7/18 ,  G11C2207/002

摘要： In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing into sectors is achieved by making use of sector select lines for selecting two or more rows of cells, and logically ANDing the sector select lines with the column select lines.

摘要翻译： 在SRAM结构中，通过提供允许使用字线和列选择线选择特定存储器单元的结构来降低功耗，并且通过将负载分成扇区来减少列地址线的负载。 通过使用用于选择两行或多行单元的扇区选择线以及逻辑地将扇区选择线与列选择线进行逻辑运算来实现划分为扇区。

公开(公告)号：US06711051B1

公开(公告)日：2004-03-23

申请号：US10235530

申请日：2002-09-05

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Weipeng Zhang ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Weipeng Zhang ,  Andrew J. Franklin

IPC分类号： G11C1100

CPC分类号： G11C11/419

摘要： A SRAM system which provides for reduced power consumption. The SRAM system utilizes an array of bit cells. Columns of bit cells in the array are partitioned into sections. Each section of bit cells shares a local bit line. A sector select circuit provides for precharging the local bit lines. The sector select circuit also includes a mux for connecting a local bit line to a global bit line. The sector select circuit includes a device for detecting when a sector select signal and a column select signal are present. When both of these signals are present the sector select circuit couples the local bit line with the global bit line, and disengages the precharging of the local bit line.

摘要翻译： 一种提供降低功耗的SRAM系统。 SRAM系统利用位单元阵列。 阵列中位单元格的列被分割成几个部分。 每个位单元共享一个本地位线。 扇区选择电路用于对本地位线进行预充电。 扇区选择电路还包括用于将局部位线连接到全局位线的多路复用器。 扇区选择电路包括用于检测何时存在扇区选择信号和列选择信号的装置。 当这两个信号都存在时，扇区选择电路将局部位线与全局位线耦合，并且使本地位线的预充电脱离。

公开(公告)号：US06621736B1

公开(公告)日：2003-09-16

申请号：US10091927

申请日：2002-03-05

申请人： Yuri Mirgorodski ,  Pavel Poplevine ,  Mark W. Poulter

发明人： Yuri Mirgorodski ,  Pavel Poplevine ,  Mark W. Poulter

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/12

摘要： A split-gate flash memory array is programmed, in part, by applying a programming voltage to the row of cells that include the to-be-programmed cells, and an inhibiting voltage to the row of cells that share the same source line as the row that includes the to-be-programmed cells. The inhibiting voltage is greater than zero and less than the programming voltage.

摘要翻译： 分割栅极闪存阵列部分地通过将编程电压施加到包括待编程单元的单元行，以及与该单元阵列共享相同源极线的抑制电压来编程 包括要编程的单元格的行。 抑制电压大于零，小于编程电压。

公开(公告)号：US20120014183A1

公开(公告)日：2012-01-19

申请号：US12837835

申请日：2010-07-16

申请人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Ernes Ho ,  Umer Khan ,  Andrew J. Franklin

IPC分类号： G11C16/04

CPC分类号： G11C16/0466

摘要： A non-volatile memory (NVM) cell structure comprises an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

摘要翻译： 非易失性存储器（NVM）单元结构包括NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS数据晶体管和连接到数据存储节点的栅电极。

公开(公告)号：US20090129162A1

公开(公告)日：2009-05-21

申请号：US12284890

申请日：2008-09-25

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Andrew Cao ,  Ernes Ho

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Andrew Cao ,  Ernes Ho

IPC分类号： G11C16/04 ,  G11C16/06 ,  H01L21/336

CPC分类号： G11C14/00

摘要： A method of making a non-volatile memory (NVM) cell structure comprises the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.

摘要翻译： 制造非易失性存储器（NVM）单元结构的方法包括形成包括第一和第二数据节点的第一NVM单元，第二NVM单元和SRAM单元。 第一通道栅极结构连接在第一NVM单元和SRAM单元的第一数据节点之间，第一通道栅极结构响应于第一和第二状态的第一通道栅极信号以分别耦合和去耦合第一NVM单元，以及 SRAM单元。 形成第一均衡结构以连接第一通道栅极结构和第一NVM单元，并且响应于第一均衡信号将第一NVM单元连接到地。 第二通路栅极结构连接在第二NVM单元和SRAM单元的第二数据节点之间，第二通道栅极结构响应第二通路栅极信号的第一和第二状态，以分别耦合和去耦合第二NVM单元，以及 SRAM单元。 第二均衡结构连接在第二通路栅极结构和第二NVM单元之间，第二均衡结构响应于第二均衡信号将第二NVM单元连接到地。 将适当的偏置条件应用于NVM单元结构以实现程序/操作。

公开(公告)号：US07126866B1

公开(公告)日：2006-10-24

申请号：US10215699

申请日：2002-08-10

申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang Lin ,  Andrew J. Franklin

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/12

摘要： In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the pre-discharging circuit during reading, only the bit line corresponding to the memory location being read.

摘要翻译： 在ROM结构中，通过仅对与正在读取的存储器位置相对应的位线进行预放电来降低功耗。 列选择线耦合到逻辑以在读取之前切换预放电电路，并且在读取期间从预放电电路断开，仅读取对应于存储器位置的位线。

公开(公告)号：US07020027B1

公开(公告)日：2006-03-28

申请号：US10895712

申请日：2004-07-08

申请人： Pavel Poplevine ,  Yuri Mirgorodski ,  Andrew J. Franklin ,  Peter J. Hopper

发明人： Pavel Poplevine ,  Yuri Mirgorodski ,  Andrew J. Franklin ,  Peter J. Hopper

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.

公开(公告)号：US06618282B1

公开(公告)日：2003-09-09

申请号：US10213845

申请日：2002-08-07

申请人： Pavel Poplevine ,  Hengyang Lin ,  Andrew J. Franklin ,  Umer Ahmed Khan

发明人： Pavel Poplevine ,  Hengyang Lin ,  Andrew J. Franklin ,  Umer Ahmed Khan

IPC分类号： G11C1700

CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C17/12

摘要： A ROM system which provides for reduced size and power consumption. This ROM systems allows for inverting the programming and sensing of information in bit cells of the ROM to reduce the number of transistors in bit cells of the ROM. Further bit cells of the ROM provide that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed.

摘要翻译： 一种提供减小尺寸和功耗的ROM系统。 该ROM系统允许反转ROM的位单元中的信息的编程和感测以减少ROM的位单元中的晶体管的数量。 ROM的其它位单元提供了当晶体管设置在位线和字线之间时，第一类型的信息被存储在位单元中，并且当第二类型的信息在 位线和字线。 在晶体管形成在位线和字线之间的情况下，在位单元中提供位线和可以在衬底中形成晶体管漏极的区域之间的接触。 在位单元在字线和位线之间不提供晶体管的情况下，在位线和可以形成晶体管漏极的区域之间不提供接触。

公开(公告)号：US06285590B1

公开(公告)日：2001-09-04

申请号：US09605291

申请日：2000-06-28

申请人： Pavel Poplevine ,  Jasopin Lee ,  Derek Tao

发明人： Pavel Poplevine ,  Jasopin Lee ,  Derek Tao

IPC分类号： G11C1134

CPC分类号： G11C7/062 ,  G11C2207/005

摘要： A low power consumption semiconductor memory circuit that includes a memory core (e.g., a ROM core) with a plurality of intersecting bit lines and word lines, as well as a plurality of memory cells at predetermined intersections of the bit and word lines. The low power consumption semiconductor memory circuit also includes a pre-discharge circuit, a multiplexer circuit (MUX), and a sense amplifier circuit. The pre-discharge circuit is electrically connected to the memory core and configured for discharging each of the bit lines to ground (GND). The MUX circuit is electrically connected to the pre-discharge circuit and configured for selecting at least one of the bit lines as its input. Furthermore, the sense amplifier circuit is configured for sensing an electrical state of an output node of the MUX circuit and, in one embodiment, includes a current generator circuit configured to charge a pre-discharged bit line during a READ operation. Low current and power consumption is achieved during operation by pre-discharging (instead of pre-charging) bit lines of the memory core to ground (GND) prior to a READ operation. Thereafter, during a READ operation, the low power consumption semiconductor memory circuits use a sense amplifier circuit and, for example, an associated reference voltage input to sense changes in the electrical state (e.g., voltage state) of a bit line that has been selected by the MUX circuit.

摘要翻译： 一种低功耗半导体存储器电路，其包括具有多个相交位线和字线的存储器核心（例如，ROM核心），以及位和字线的预定交叉点处的多个存储器单元。 低功耗半导体存储器电路还包括预放电电路，多路复用器电路（MUX）和读出放大器电路。 预放电电路电连接到存储器芯并且被配置为将每个位线放电到地（GND）。 MUX电路电连接到预放电电路并且被配置用于选择位线中的至少一个作为其输入。 此外，感测放大器电路被配置为感测MUX电路的输出节点的电状态，并且在一个实施例中，包括配置成在READ操作期间对预放电位线充电的电流发生器电路。 在读取操作之前，通过将存储器芯线的位线预先放电（而不是预充电）到地（GND）来实现低电流和功耗。 此后，在READ操作期间，低功耗半导体存储器电路使用读出放大器电路和例如相关联的参考电压输入来检测已选择的位线的电状态（例如，电压状态）的变化 由MUX电路。