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    Non-volatile memory cell with improved programming technique
    4.
    发明授权
    Non-volatile memory cell with improved programming technique 有权
    具有改进编程技术的非易失性存储单元

    公开(公告)号：US07167392B1

    公开(公告)日：2007-01-23

    申请号：US11183198

    申请日：2005-07-15

    申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

    IPC分类号： G11C11/34 ,  G11C14/00 ,  G11C16/04

    CPC分类号： G11C14/00 ,  G11C7/06 ,  G11C16/0408

    摘要： A non-volatile memory (NVM) cell splits its basic function, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell. The programming method for the cell utilizes a reverse Fowler-Nordheim tunneling mechanism with a very small programming current, allowing an entire NVM array to be programmed at one cycle.

    摘要翻译： 非易失性存储器（NVM）单元在四个PMOS晶体管结构中分离其基本功能，即编程，擦除，读取和控制，允许每个功能的独立优化。 单元结构还包括嵌入式静态随机存取存储器（SRAM）单元，其利用锁存结构来预编程要写入单元的数据。 该单元的编程方法利用具有非常小的编程电流的反向Fowler-Nordheim隧道机制，允许在一个周期对整个NVM阵列进行编程。

    All-NMOS 4-transistor non-volatile memory cell
    5.
    发明授权
    All-NMOS 4-transistor non-volatile memory cell 有权
    全NMOS 4晶体管非易失性存储单元

    公开(公告)号：US08363469B1

    公开(公告)日：2013-01-29

    申请号：US12698318

    申请日：2010-02-02

    申请人： Pavel Poplevine ,  Umer Khan ,  Hengyang (James) Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Umer Khan ,  Hengyang (James) Lin ,  Andrew J. Franklin

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： H01L27/115

    摘要： A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.

    摘要翻译： 非易失性存储单元包括具有连接到存储节点的栅极的NMOS编程，读取，擦除和控制晶体管。 擦除和控制晶体管具有互连的源极，漏极和体电极。 通过将所有晶体管的源极，漏极，体积和栅极电极设置为正电压来对单元进行编程。 在将编程晶体管的源极和漏极电极设置为正电压和编程晶体管的体电极至正电压或抑制电压的同时，将读取晶体管的源极，漏极和体电极施加抑制电压。 然后，控制晶体管的源极，漏极和体电极斜坡到负的控制电压，同时将擦除晶体管的源极，漏极和体电极斜缓到负的擦除电压，然后返回到正的电压。 来源，流失。 然后将编程，擦除和控制晶体管的体积和栅电极返回到正电压，同时将读取晶体管的源极，漏极和体电极设置为抑制电压。

    4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE
    6.
    发明申请
    4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE 有权
    具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元

    公开(公告)号：US20110242898A1

    公开(公告)日：2011-10-06

    申请号：US12751012

    申请日：2010-03-31

    申请人： Pavel Poplevine ,  Ernes Ho ,  Hengyang James Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Ernes Ho ,  Hengyang James Lin ,  Andrew J. Franklin

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/0441 ,  G11C16/10

    摘要： A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.

    摘要翻译： 非易失性存储器（NVM）单元结构包括具有源极，漏极和体区电极的PMOS程序晶体管和连接到数据存储节点的栅电极; NMOS控制晶体管，其具有共同连接以接收控制电压的源极，漏极和体区电极以及连接到数据存储节点的栅电极; PMOS擦除晶体管，其具有共同连接以接收擦除电压的源极，漏极和体区电极;以及连接到数据存储节点的栅电极; 以及具有源极，漏极和体区电极的NMOS读取晶体管和连接到数据存储节点的栅电极。

    Anti-pirate circuit for protection against commercial integrated circuit pirates
    9.
    发明授权
    Anti-pirate circuit for protection against commercial integrated circuit pirates 有权
    反海盗电路，用于防止商业集成电路海盗

    公开(公告)号：US07558969B1

    公开(公告)日：2009-07-07

    申请号：US10383416

    申请日：2003-03-06

    申请人： Elroy M. Lucero ,  Daniel J. Lucero ,  Hengyang (James) Lin ,  Andrew J. Franklin ,  Pavel Poplevine

    发明人： Elroy M. Lucero ,  Daniel J. Lucero ,  Hengyang (James) Lin ,  Andrew J. Franklin ,  Pavel Poplevine

    IPC分类号： G06F11/07

    CPC分类号： G06F21/73

    摘要： Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.

    摘要翻译： 提供反盗版电路，用于防止半导体集成电路中包含的知识产权被盗。 反盗版电路包括唯一的数字发生器，其提供与反盗版电路相关联的集成电路所独有的多位芯片ID数据串。 一次可编程（OTP）EPROM电路读取晶片分类中的芯片ID数据串，并将数据内容写入非易失性存储器。 在随后的验证周期中，ID比较器电路将由唯一编号发生器提供的数据串与非易失性存储器的存储内容进行比较。 如果比较导致超过预定数量的比特之间的不匹配，则与反盗版电路相关联的集成电路不能被使能以进行操作。

    Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle
    10.
    发明授权
    Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle 有权
    在单个周期中对非易失性存储器（NVM）单元阵列进行热电子注入编程的方法

    公开(公告)号：US07239558B1

    公开(公告)日：2007-07-03

    申请号：US11235834

    申请日：2005-09-26

    申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

    发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang Lin ,  Andrew J. Franklin

    IPC分类号： G11C11/34

    CPC分类号： G11C11/005 ,  G11C14/00 ,  G11C16/0441

    摘要： A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell and a plurality of cascoded NMOS pass gates. The cell structure reduces total programming time and provides the flexibility of programming the entire cell array simultaneously or one row or sector of the array at a time.

    摘要翻译： 非易失性存储器（NVM）单元在四个PMOS晶体管结构中分离其基本功能，即编程，擦除，读取和控制，允许每个单元功能的独立优化。 单元结构还包括嵌入式静态随机存取存储器（SRAM）单元，其利用锁存结构来预编程要写入单元的数据和多个级联的NMOS通道门。 单元结构减少总编程时间，并提供同时编程整个单元阵列或阵列的一行或多个扇区的灵活性。