公开(公告)号：US5741741A

公开(公告)日：1998-04-21

申请号：US652175

申请日：1996-05-23

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/31144 ,  H01L21/76813

摘要： A method for making planar metal interconnections and T-shaped metal plugs for integrated circuits is achieved. The method involves forming a planar insulating (SiO.sub.2) and a hard mask film over a first level of interconnections. A patterned first photoresist layer is then formed for etching trenches in the hard mask film and partially into the planar insulating layer (SiO.sub.2) in which a second level of interconnections are to be formed. The patterned photoresist layer is then laterally etched to expose the hard mask adjacent to the trenches in the SiO.sub.2, and the hard mask is then removed adjacent to the trenches to form a self-aligned mask for the metal plug contact openings. A patterned second photoresist mask aligned over the trenches is then used to etch the contact openings in the trenches, using the hard mask to form T-shaped plug contact openings to the first level of interconnections. The trenches and plug contact openings are concurrently filled with CVD aluminum and chem/mech polished back to form the second level of interconnections with T-shaped metal plugs. The T-shaped metal plugs improve the edge coverage while making it easier to fill the narrow contact openings with aluminum without voids in the metal plugs.

摘要翻译： 实现了用于集成电路的平面金属互连和T形金属插头的方法。 该方法包括在第一级互连上形成平面绝缘（SiO 2）和硬掩模膜。 然后形成图案化的第一光致抗蚀剂层，用于蚀刻硬掩模膜中的沟槽，并部分地形成将要形成第二级互连的平面绝缘层（SiO 2）。 然后横向蚀刻图案化的光致抗蚀剂层以暴露与SiO 2中的沟槽相邻的硬掩模，然后邻近沟槽移除硬掩模以形成用于金属插头接触开口的自对准掩模。 然后使用在沟槽上对准的图案化的第二光致抗蚀剂掩模来蚀刻沟槽中的接触开口，使用硬掩模形成到第一级互连的T形插头接触开口。 沟槽和插头接触开口同时填充有CVD铝和化学/机械抛光，以形成与T形金属插头的第二级互连。 T形金属插头提高边缘覆盖率，同时更容易用铝填充狭窄的接触开口，而在金属插头中无空隙。

公开(公告)号：US5731130A

公开(公告)日：1998-03-24

申请号：US747500

申请日：1996-11-12

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  B03C5/00 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91 ,  H01L28/92 ,  Y10S438/948

摘要： A method for manufacturing an array of stacked capacitors with increased capacitance for DRAM devices was achieved. The invention utilizes two photoresist masking steps and a series of self-aligning etch back steps to form a very high density array of bottom capacitor (node) electrodes. The method involves depositing and planarizing an insulating layer over the DRAM cell areas in which node contact openings (first photoresist mask) are etched to the node contact areas of the FETs. A polysilicon layer is deposited, filling the node contact openings, and patterned (second photoresist mask) to define the outer perimeters of bottom electrodes and the polysilicon layer is recessed by partially plasma etching. The second patterned photoresist mask is then laterally recessed by ashing in O.sub.2 to expose the polysilicon. A second anisotropic etch is used to form a bottom electrode having a vertical center portion and a wider base area. A conformal insulating layer is deposited and etched back to form sidewall spacers followed by a polysilicon deposition and etch back to form vertical portions on the electrode. The capacitors are then completed by removing (etching) the spacer and portions of the planar underlying layer and forming an interelectrode dielectric on the bottom electrodes and patterning another polysilicon layer to form the top electrodes.

摘要翻译： 实现了一种用于制造具有增加的用于DRAM器件的电容的堆叠电容器阵列的方法。 本发明利用两个光致抗蚀剂掩模步骤和一系列自对准回蚀步骤来形成底部电容器（节点）电极的非常高密度阵列。 该方法包括在其中将节点接触开口（第一光致抗蚀剂掩模）蚀刻到FET的节点接触区域的DRAM单元区域上沉积和平坦化绝缘层。 沉积多晶硅层，填充节点接触开口和图案化（第二光致抗蚀剂掩模）以限定底部电极的外周边，并且多晶硅层通过部分等离子体蚀刻凹陷。 然后第二图案化的光致抗蚀剂掩模通过在O 2中的灰化而横向凹陷以暴露多晶硅。 使用第二种各向异性蚀刻来形成具有垂直中心部分和较宽基底面积的底部电极。 将保形绝缘层沉积并回蚀刻以形成侧壁间隔物，随后进行多晶硅沉积并回蚀刻以在电极上形成垂直部分。 然后通过去除（蚀刻）间隔物和平面下层的部分并在底部电极上形成电极间电介质并构图另一多晶硅层以形成顶部电极来完成电容器。

公开(公告)号：US5716883A

公开(公告)日：1998-02-10

申请号：US746060

申请日：1996-11-06

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, consisting of an upper polysilicon shape, comprised of polysilicon columns, with a narrow space between polysilicon columns, and an underlying lower polysilicon shape, residing in a contact hole, and making contact to underlying transistor regions. The polysilicon columns, and the narrow space, between polysilicon columns are formed via creation of a narrow trench in a top portion of a polysilicon layer, followed by an anisotropic etch to create the exterior shape of the storage node electrode. A key feature of this invention is the use of a photoresist plug, in the trench, used to protect the lower portion of the storage node electrode during the exterior shape, patterning process. This storage node electrode configuration results in increased surface area, via use of polysilicon columns, as well as density improvements, resulting from the use of narrow spaces between polysilicon columns.

摘要翻译： 已经开发了用于高密度DRAM设计的STC结构的创建方法。 该过程包括为STC结构创建一个存储节点电极，其由多晶硅柱构成，上部多晶硅形状由多晶硅柱组成，多晶硅柱之间具有窄空间，并且位于接触孔中的下层多晶硅形状， 接触底层晶体管区域。 多晶硅柱之间的多晶硅柱和窄空间通过在多晶硅层的顶部部分中产生窄沟槽，随后进行各向异性蚀刻来形成存储节点电极的外部形状。 本发明的一个关键特征是使用在沟槽中的光致抗蚀剂插塞，用于在外部形状，图案化工艺期间保护存储节点电极的下部。 这种存储节点电极结构通过使用多晶硅柱而导致增加的表面积，以及由于在多晶硅柱之间使用窄空间而导致的密度改善。

公开(公告)号：US5705438A

公开(公告)日：1998-01-06

申请号：US735061

申请日：1996-10-18

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/8242 ,  H01L21/8234

CPC分类号： H01L27/10852

摘要： A method for manufacturing stacked dynamic random access memory using reduced photomask steps was achieved. The invention utilizes two masking steps for forming the array of stacked capacitors and bit line contacts. One of the masking steps is used to concurrently form the bit line contact openings and to define the capacitor top electrode area for the stacked capacitors. After forming the array of field effect transistors by conventional means, an array of capacitor bottom electrodes is patterned from an N.sup.+ doped polysilicon layer using the first photoresist mask and plasma etching. An interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped second poly-silicon layer and insulating layer are deposited. The insulating layer and second polysilicon layer are patterned with a second photoresist mask and plasma etched to concurrently form the bit line contact openings and to define the capacitor top electrode plate. The sidewalls of the exposed second polysilicon layer in the bit line contact openings are then oxidized to prevent the top electrode plate from shorting to the bit lines which are then patterned from a polycide layer that extends over and in the bit line contact openings.

摘要翻译： 实现了使用降低的光掩模步骤来制造堆叠的动态随机存取存储器的方法。 本发明利用两个掩模步骤来形成叠层电容器阵列和位线接触。 掩模步骤之一用于同时形成位线接触开口并且限定用于层叠电容器的电容器顶部电极区域。 在通过常规方法形成场效应晶体管阵列之后，使用第一光致抗蚀剂掩模和等离子体蚀刻从N +掺杂多晶硅层图案化电容器底部电极的阵列。 在底部电极上形成电极间电介质层。 沉积N +掺杂的第二多晶硅层和绝缘层。 绝缘层和第二多晶硅层用第二光致抗蚀剂掩模图案化，等离子体蚀刻以同时形成位线接触开口并限定电容器顶部电极板。 然后，位线接触开口中的暴露的第二多晶硅层的侧壁被氧化，以防止顶部电极板与位线短路，然后从位线延伸并在位线接触开口中延伸出多晶硅化物层。

公开(公告)号：US5693562A

公开(公告)日：1997-12-02

申请号：US672450

申请日：1996-06-28

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/312

CPC分类号： H01L21/76865 ,  H01L21/76843

摘要： A method for forming a barrier metal film with conformal step coverage in a semiconductor integrated circuit includes forming a photoresist plug in a barrier metal lined contact or via hole. The barrier metal film has an overhang that narrows the opening to the contact or via hole. The barrier metal film is then etched using a fluorine based plasma etch process to remove the overhang. The photoresist plug is then removed using a oxygen based plasma etch process. The contact or via hole is then filled with tungsten to form a tungsten plug.

摘要翻译： 在半导体集成电路中形成具有适形步骤覆盖的阻挡金属膜的方法包括在阻挡金属衬里的接触或通孔中形成光致抗蚀剂插塞。 阻挡金属膜具有使接触孔或通孔开口变窄的突出端。 然后使用氟基等离子体蚀刻工艺蚀刻阻挡金属膜以去除突出端。 然后使用氧等离子体蚀刻工艺除去光致抗蚀剂插塞。 然后用钨填充接触孔或通孔，形成钨丝塞。

公开(公告)号：US5688706A

公开(公告)日：1997-11-18

申请号：US691290

申请日：1996-08-01

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/66583 ,  H01L21/28061 ,  H01L29/1033 ,  H01L29/4925 ,  H01L29/66537 ,  H01L29/7833

摘要： A process has been developed in which a deep submicron MOSFET device has been fabricated, featuring a local, narrow threshold voltage adjust region, in a semiconductor substrate, with the local, narrow threshold voltage adjust region, self aligned to an overlying, narrow tungsten-polysilicon gate structure. The process consists of forming a narrow hole opening in an insulator layer, where the insulator layer overlies a polysilicon layer and a gate insulator layer. An ion implantation procedure, through the polysilicon layer, and gate insulator layer, is used to place a narrow threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. Selective deposition of tungsten results in the creation of a tungsten gate structure, in the narrow hole opening, on the top surface of the polysilicon layer. Patterning of the polysilicon layer, using the overlying tungsten gate structure as a mask, results in an polysilicon gate structure, underlying the tungsten gate structure, in the narrow hole opening. The composite narrow tungsten-polysilicon gate structure is self aligned to the underlying, local, narrow threshold voltage adjust region.

摘要翻译： 已经开发了一种方法，其中已经制造了深亚微米MOSFET器件，其特征在于在半导体衬底中具有局部，窄阈值电压调整区域，具有局部，窄阈值电压调整区域，与上覆窄的钨 - 多晶硅栅结构。 该方法包括在绝缘体层中形成窄孔开口，其中绝缘体层覆盖多晶硅层和栅极绝缘体层。 使用通过多晶硅层和栅极绝缘体层的离子注入工艺将窄阈值电压调整区域放置在半导体衬底的特定区域中，位于窄孔开口下方。 钨的选择性沉积导致在多孔层的顶表面上的窄孔开口中产生钨栅极结构。 使用覆盖钨栅结构作为掩模的多晶硅层的图案化导致窄孔开口中的钨栅极结构下方的多晶硅栅极结构。 复合窄钨多晶硅栅极结构与底层，局部，窄阈值电压调整区域自对准。

公开(公告)号：US5677222A

公开(公告)日：1997-10-14

申请号：US728703

申请日：1996-10-11

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： An improved method for forming a dynamic random access memory (DRAM) capacitor with increased capacitance is disclosed. The method includes forming an oxide layer on a semiconductor substrate with a metal-oxide-semiconductor field effect transistor (MOSFET) conventionally formed therein and thereon. A planarized silicon nitride layer is then formed on the oxide layer. Then alternating layers of dielectric layers having different etch rates are formed on the silicon nitride layer. Standard photolithographic methods are used to etch a trench through the dielectric layers and the silicon nitride layer to expose the source region of the MOSFET. The trench is then isotropically etched, forming rounded cavities in portions of the dielectric layers having the faster etch rate. The rounded cavities extend horizontally into the sidewalls of the trench. A doped polysilicon layer is then formed on the top of the dielectric layers so as to fill the trench and the rounded cavities. The polysilicon layer is then patterned and etched to removed the polysilicon layer around the trench. The dielectric layers are then removed, thereby forming the bottom electrode of a DRAM cell capacitor.

摘要翻译： 公开了一种用于形成具有增加的电容的动态随机存取存储器（DRAM）电容器的改进方法。 该方法包括在半导体衬底上形成氧化层，其上通常形成有金属氧化物半导体场效应晶体管（MOSFET）。 然后在氧化物层上形成平坦化的氮化硅层。 然后在氮化硅层上形成具有不同蚀刻速率的电介质层的交替层。 使用标准光刻方法蚀刻通过介电层和氮化硅层的沟槽，以暴露MOSFET的源极区域。 然后各向同性蚀刻沟槽，在具有更快蚀刻速率的电介质层的部分中形成圆形空腔。 圆形空腔水平延伸到沟槽的侧壁。 然后在电介质层的顶部上形成掺杂的多晶硅层，以便填充沟槽和圆形空腔。 然后对多晶硅层进行图案化和蚀刻以去除沟槽周围的多晶硅层。 然后去除电介质层，从而形成DRAM单元电容器的底部电极。

公开(公告)号：US5677217A

公开(公告)日：1997-10-14

申请号：US691287

申请日：1996-08-01

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/66583 ,  H01L21/28282 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/66537

摘要： A process has been developed in which a deep submicron MOSFET device has been fabricated, featuring a local, narrow threshold voltage adjust region, in a semiconductor substrate, with the narrow threshold voltage adjust region, self aligned to an overlying, narrow, polycide gate structure. The process consists of forming a narrow hole opening in an insulator layer, where the insulator layer overlies a polysilicon layer and a gate insulator layer. An ion implantation procedure, through the polysilicon layer, and gate insulator layer, is used to place a narrow threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. Deposition of a metal layer, followed by an anneal procedure, converts the top portion of polysilicon, in the narrow hole opening, to a metal silicide structure. After removal of unreacted metal, and insulator layer, the polysilicon layer is patterned, via RIE procedures, using the metal silicide structure as a mask, to create a narrow polycide gate structure, comprised of an overlying, narrow metal silicide gate, and an underlying, narrow polysilicon gate structure. The narrow polycide gate structure is self aligned to the underlying, narrow threshold voltage adjust region.

摘要翻译： 已经开发了一种工艺，其中在半导体衬底中制造了具有局部，窄阈值电压调整区域的深亚微米MOSFET器件，其具有窄的阈值电压调整区域，与上覆的窄的多选择栅极结构自对准 。 该方法包括在绝缘体层中形成窄孔开口，其中绝缘体层覆盖多晶硅层和栅极绝缘体层。 使用通过多晶硅层和栅极绝缘体层的离子注入工艺将窄阈值电压调整区域放置在半导体衬底的特定区域中，位于窄孔开口下方。 沉积金属层，然后进行退火处理，将窄孔开口中的多晶硅顶部转化为金属硅化物结构。 在去除未反应的金属和绝缘体层之后，通过RIE工艺，使用金属硅化物结构作为掩模来对多晶硅层进行构图，以形成窄的多晶硅栅极结构，其由上覆的窄金属硅化物栅极和底层 ，窄多晶硅栅极结构。 窄的多晶硅栅极结构与下面的窄阈值电压调整区域自对准。

公开(公告)号：US5670407A

公开(公告)日：1997-09-23

申请号：US791507

申请日：1997-01-30

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/92 ,  Y10S438/947

摘要： The present invention is a method of fabricating a toothed-shape capacitor node in a semiconductor DRAM circuit. This invention utilizes dot silicon as an etching mask. Next, the polysilicon is oxidized and removed to form trenches in the bottom storage of the capacitor. Thus, a toothed-shape capacitor node is formed in semiconductor circuit.

摘要翻译： 本发明是在半导体DRAM电路中制造齿形电容器节点的方法。 本发明利用点硅作为蚀刻掩模。 接下来，多晶硅被氧化并去除，以在电容器的底部存储器中形成沟槽。 因此，在半导体电路中形成齿形电容器节点。

公开(公告)号：US5670405A

公开(公告)日：1997-09-23

申请号：US791504

申请日：1997-01-30

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/70

CPC分类号： H01L28/92 ,  Y10S148/138

摘要： A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming a silicon oxide layer as an etching mask to etch a polysilicon layer to form a bottom storage node of a capacitor. The silicon oxide layer is formed from the thermal annealing of oxygen doped dot silicon.

摘要翻译： 本文公开了制造用于半导体存储器的电容器的方法。 本发明包括形成氧化硅层作为蚀刻掩模以蚀刻多晶硅层以形成电容器的底部存储节点。 氧化硅层由氧掺杂点硅的热退火形成。