公开(公告)号：US20150358008A1

公开(公告)日：2015-12-10

申请号：US14300119

申请日：2014-06-09

Applicant: Qualcomm Incorporated

Inventor： Li Sun ,  Zhi Zhu ,  Xiaohua Kong

IPC: H03K5/13 ,  H04L7/02

CPC classification number: H03K5/13 ,  H03K2005/00052 ,  H03K2005/00286 ,  H04L7/0025 ,  H04L7/02

Abstract: A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches.

Abstract translation: 一种相位插值器，包括：耦合到电源电压的一对负载电阻; 耦合到所述一对负载电阻器的多个分支，每个分支包括在源极端子处连接以形成源节点的差分对晶体管; 多个尾流源，每个尾电流源耦合到源节点之一; 以及多个耦合电容器，每个耦合电容器耦合在所述多个分支的两个相邻分支中的源节点之间。

公开(公告)号：US20150235952A1

公开(公告)日：2015-08-20

申请号：US14703240

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Yuancheng Christopher Pan ,  Fifin Sweeney ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

IPC: H01L23/538 ,  H05K1/16 ,  H05K1/18 ,  H05K1/11 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/02 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02371 ,  H01L2224/05624 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/11 ,  H05K1/165 ,  H05K1/181 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

Abstract translation: 堆叠式集成电路包括第一层IC和第二层IC。 第一层IC和第二层IC的主动面相互面对。 互连结构，例如microbumps，将第一层IC耦合到第二层IC。 电压调节器的有源部分集成在第一半导体IC中并耦合到嵌入在其上安装有堆叠IC的封装衬底中的无源组件（例如，电容器或电感器）。 无源部件可以是在封装衬底中的多个通孔，为电压调节器的有源部分提供电感。 通过将封装衬底中的通孔耦合到安装有封装衬底的印刷电路板中的通孔，增加了提供给电压调节器的有源部分的电感。