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1.发明授权公开(公告)号：US11863356B2
公开(公告)日：2024-01-02
申请号：US17589782
申请日：2022-01-31
发明人： Miao Li , Zhiqin Chen , Yu Song , Hongmei Liao , Zhi Zhu , Hao Liu , Lejie Lu
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L25/03885
摘要： A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.
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公开(公告)号：US10698439B1
公开(公告)日：2020-06-30
申请号：US16413292
申请日：2019-05-15
发明人： Li Sun , Russell Deans , Zhiqin Chen , Zhi Zhu
摘要： In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.
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3.发明申请公开(公告)号：US20180349311A1
公开(公告)日：2018-12-06
申请号：US16058251
申请日：2018-08-08
发明人： Zhi Zhu , Xiaohua Kong , Nir Gerber , Christian Josef Wiesner
CPC分类号： G06F13/4282 , G06F13/36 , G06F13/387 , G06F13/4022 , G06F13/4068 , G06F13/4072 , G06F13/4086
摘要： An apparatus and methods are disclosed for a bidirectional front-end circuit included within a system on chip (SoC). The bidirectional front-end circuit includes a differential bidirectional terminal for receiving and transmitting signals. The bidirectional front-end circuit is configured to provide a first communication path between a first controller and a connector through the differential bidirectional terminal when operating in a first mode. And, the bidirectional front-end circuit is reconfigured to provide a second communication path between a second controller and the connector through the differential bidirectional terminal when operating in a second mode.
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公开(公告)号：US09829958B1
公开(公告)日：2017-11-28
申请号：US15150586
申请日：2016-05-10
IPC分类号： G06F1/32
CPC分类号： G06F1/3278 , G06F1/3209 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/3253 , G06F1/3287
摘要： Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.
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公开(公告)号：US09264263B2
公开(公告)日：2016-02-16
申请号：US14257848
申请日：2014-04-21
发明人： Madjid Hafizi , Xiaohua Kong , Zhi Zhu , Miao Li
IPC分类号： H04B3/00 , H04L25/02 , H04L7/00 , H03K5/12 , H03K19/0185
CPC分类号： H04L25/0276 , H03K5/12 , H03K19/018528 , H04L7/0091
摘要： A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers.
摘要翻译： 用于在通信链路上发送串行数据的驱动器电路组合电压模式和电流模式驱动器。 驱动电路使用电压模式驱动器作为主输出驱动器。 一个或多个辅助电流模式驱动器与电压模式驱动器并联连接，以通过向输出中注入电流来调整输出信号。 电压模式驱动器提供大部分输出驱动器。 因此，输出驱动器电路可以提供与电压模式驱动器相关联的功率效率益处。 电流模式驱动器可以提供例如预加重，电平调整，偏斜补偿和输出信号的其它修改。 因此，驱动器电路还可以提供与当前模式驱动器相关联的信号调节能力。
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6.发明授权公开(公告)号：US11646917B1
公开(公告)日：2023-05-09
申请号：US17563989
申请日：2021-12-28
发明人： Younwoong Chung , Yu Song , Minghsien Tsai , Zhi Zhu
CPC分类号： H04L25/03057 , H04L7/0079 , H04L7/04
摘要： An equalizing circuit includes a first current summer that receives a data signal and a first plurality of feedback signals, a first multiplexer that selects a first sampling clock signal from a plurality of clock signals using a signal that indicates a mode of operation of the equalizing circuit, and a first slicer that samples the output of the first current summer in accordance with timing provided by the first sampling clock signal. The equalizing circuit can have a second current summer that receives the data signal and a second plurality of feedback signals, a second multiplexer that selects a second sampling clock signal from the plurality of clock signals using the signal that indicates the mode of operation of the equalizing circuit, and a second slicer that samples the output of the second current summer according to timing provided by the second sampling clock signal.
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公开(公告)号：US11349445B2
公开(公告)日：2022-05-31
申请号：US17017239
申请日：2020-09-10
摘要： A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.
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公开(公告)号：US20180219704A1
公开(公告)日：2018-08-02
申请号：US15422050
申请日：2017-02-01
发明人： Yu Song , Zhi Zhu , Miao Li , Li Sun , Deqiang Song , Chia Heng Chang
CPC分类号： H04L25/03273 , H03L7/0814 , H04L7/0025 , H04L7/0337 , H04L43/16 , H04L2027/0069
摘要： Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).
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公开(公告)号：US20170329386A1
公开(公告)日：2017-11-16
申请号：US15150586
申请日：2016-05-10
CPC分类号： G06F1/3278 , G06F1/3209 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/3253 , G06F1/3287
摘要： Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.
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10.发明授权Linearity of phase interpolators by combining current coding and size coding 有权通过组合当前编码和大小编码来实现相位内插器的线性度公开(公告)号：US09485084B2
公开(公告)日：2016-11-01
申请号：US14300127
申请日：2014-06-09
发明人： Li Sun , Zhi Zhu , Xiaohua Kong , Kenneth Luis Arcudia , Zhiqin Chen
CPC分类号： H04L7/0331 , H03K5/135 , H03K2005/00065 , H03L7/099
摘要： A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.
摘要翻译： 一种相位插值器，包括：包括第一多个分支和多个尾电流源的第一部分，每个分支包括差分对晶体管，所述差分对晶体管的源极端子连接以形成源节点，其中每个尾部 电流源耦合到源节点之一，并且其中所述差分对晶体管和相应的尾电流源以当前编码方案配置; 第二部分包括第二多个分支和耦合到第二多个分支的固定电流源，第二多个分支的每个分支包括第二多个差分对晶体管和多个开关，其以尺寸编码方案 ; 其中所述第一部分和所述第二部分彼此耦合并耦合到一对负载电阻器。
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