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    High-speed sense amplifier with a dynamically cross-coupled regeneration stage
    1.
    发明授权
    High-speed sense amplifier with a dynamically cross-coupled regeneration stage 有权

    公开(公告)号：US11095273B1

    公开(公告)日：2021-08-17

    申请号：US16940280

    申请日：2020-07-27

    Applicant: QUALCOMM Incorporated

    Inventor： Todd Morgan Rasmus ,  Li Sun ,  Dong Ren

    IPC: H03K3/037 ,  H04L25/03 ,  G11C7/06 ,  H03K5/24 ,  H03M9/00

    Abstract: In certain aspects, a regenerative stage of a sense amplifier includes a first inverter having an input and an output, and a second inverter having an input and an output. The regenerative stage also includes a third inverter having an input, an output coupled to the input of the second inverter, a first supply terminal coupled to a supply rail, and a second supply terminal coupled to the output of the first inverter. The regenerative stage further includes a fourth inverter having an input, an output coupled to the input of the first inverter, a first supply terminal coupled to the supply rail, and a second supply terminal coupled to the output of the second inverter.

    Multi-mode phase-frequency detector for clock and data recovery
    2.
    发明授权
    Multi-mode phase-frequency detector for clock and data recovery 有权
    多模相位频率检测器，用于时钟和数据恢复

    公开(公告)号：US09485082B1

    公开(公告)日：2016-11-01

    申请号：US14747789

    申请日：2015-06-23

    Applicant: QUALCOMM Incorporated

    Inventor： Li Sun ,  Zhi Zhu ,  Miao Li ,  Xiaohua Kong

    IPC: H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/0025 ,  H03L7/0807 ,  H04L7/033 ,  H04L7/0337

    Abstract: A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.

    Abstract translation: 时钟和数据恢复（CDR）电路产生同相时钟，与同相时钟偏移90度的正交时钟，以及从同相时钟偏移90度的辅助时钟偏移。 数据采样器根据同相，正交和辅助时钟周期性地采样数据信号以形成采样组，每个组包括同相采样，正交采样和辅助采样。 CDR逻辑电路处理样本以形成每组的定时字。

    Linearity of phase interpolators using capacitive elements
    4.
    发明授权
    Linearity of phase interpolators using capacitive elements 有权
    使用电容元件的相位内插器的线性度

    公开(公告)号：US09356588B2

    公开(公告)日：2016-05-31

    申请号：US14300119

    申请日：2014-06-09

    Applicant: Qualcomm Incorporated

    Inventor： Li Sun ,  Zhi Zhu ,  Xiaohua Kong

    IPC: H03H11/16 ,  H03K5/13 ,  H04L7/02 ,  H04L7/00 ,  H03K5/00

    CPC classification number: H03K5/13 ,  H03K2005/00052 ,  H03K2005/00286 ,  H04L7/0025 ,  H04L7/02

    Abstract: A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches.

    Abstract translation: 一种相位插值器，包括：耦合到电源电压的一对负载电阻; 耦合到所述一对负载电阻器的多个分支，每个分支包括在源极端子处连接以形成源节点的差分对晶体管; 多个尾流源，每个尾电流源耦合到源节点之一; 以及多个耦合电容器，每个耦合电容器耦合在所述多个分支的两个相邻分支中的源节点之间。

    Pulse-width modulation data decoder
    5.
    发明授权
    Pulse-width modulation data decoder 有权
    脉宽调制数据解码器

    公开(公告)号：US09203391B2

    公开(公告)日：2015-12-01

    申请号：US14258980

    申请日：2014-04-22

    Applicant: QUALCOMM Incorporated

    Inventor： Zhi Zhu ,  Xiaohua Kong ,  Li Sun ,  Jie Xu

    IPC: H04L7/00 ,  H03K9/08

    CPC classification number: H03K9/08 ,  G06F13/4072 ,  H04L25/4902 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient.

    Abstract translation: 公开了用于解码脉宽调制（PWM）数据的系统和方法。 示例解码器用单向脉冲滤波器对数据输入信号进行滤波。 单面脉冲滤波器抑制数据输入信号的短脉冲，并通过长脉冲。 示例解码器在数据输入信号的每个位时间结束时锁存经滤波的数据信号。 由单侧脉冲滤波器抑制的脉冲的持续时间可被校准，以补偿电路变化并允许解码器以各种数据速率工作。 解码器可以在小的集成电路区域中实现，并且可以是功率效率的。

    Ultra-high bandwidth inductorless amplifier
    6.
    发明授权
    Ultra-high bandwidth inductorless amplifier 有权

    公开(公告)号：US11736069B2

    公开(公告)日：2023-08-22

    申请号：US17173947

    申请日：2021-02-11

    Applicant: QUALCOMM Incorporated

    Inventor： Hao Liu ,  Li Sun ,  Dong Ren

    IPC: H03F3/45 ,  H03F1/34 ,  H03F1/26

    CPC classification number: H03F1/342 ,  H03F1/26 ,  H03F3/45475 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/372

    Abstract: An amplifier has a first amplifying circuit configured to receive a voltage input and to output an amplified current, a second amplifying circuit configured to receive the amplified current and to output an amplified voltage, the second amplifying circuit comprising a pair of feedback resistive elements, each feedback resistive element being coupled to a gate and drain of a corresponding transistor in a pair of output transistors in the second amplifying circuit, and a feedback circuit configured to provide a negative feedback loop between an input and an output of the pair of output transistors, the feedback circuit including a first transconductance amplification circuit and a first equalizing circuit.

    Clock data recovery with non-uniform clock tracking
    7.
    发明授权
    Clock data recovery with non-uniform clock tracking 有权

    公开(公告)号：US10084621B2

    公开(公告)日：2018-09-25

    申请号：US15422050

    申请日：2017-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

    IPC: H03D3/18 ,  H03D3/24 ,  H04L25/03 ,  H04L12/26 ,  H04L27/00

    Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

    COMMON-GATE AMPLIFIER FOR HIGH-SPEED DC-COUPLING COMMUNICATIONS
    10.
    发明申请
    COMMON-GATE AMPLIFIER FOR HIGH-SPEED DC-COUPLING COMMUNICATIONS 有权
    用于高速直流耦合通信的通用放大器

    公开(公告)号：US20160079942A1

    公开(公告)日：2016-03-17

    申请号：US14486885

    申请日：2014-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Miao Li ,  Li Sun ,  Zhi Zhu

    IPC: H03F3/45 ,  H04B1/16 ,  H04L25/02 ,  H03F3/183

    CPC classification number: H03F3/45071 ,  H03F3/183 ,  H03F3/45179 ,  H03F3/45677 ,  H03F3/45713 ,  H03F2200/129 ,  H03F2200/255 ,  H03F2200/36 ,  H03F2200/453 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45112 ,  H03F2203/45302 ,  H03F2203/45306 ,  H03F2203/45418 ,  H03F2203/45422 ,  H03F2203/45424 ,  H04B1/16 ,  H04L25/0272

    Abstract: In one embodiment, a receiver comprises a differential common-gate amplifier having a differential input and a differential output, wherein the differential input comprises a first input and a second input, and the differential common-gate amplifier is configured to amplify an input differential signal at the differential input into an amplified differential signal at the differential output. The receiver also comprises a common-mode voltage sensor configured to sense a common-mode voltage of the input differential signal, a replica circuit configured to generate a replica voltage that tracks a direct current (DC) voltage at at least one of the first and second inputs, and a comparator configured to compare the sensed common-mode voltage with the replica voltage, and to adjust a first bias voltage input to the differential common-gate amplifier based on the comparison, wherein the DC voltage depends on the first bias voltage.

    Abstract translation: 在一个实施例中，接收机包括具有差分输入和差分输出的差分共栅放大器，其中差分输入包括第一输入和第二输入，并且差分共栅放大器被配置为放大输入差分信号 在差分输入处的差分输出处的放大的差分信号。 接收机还包括被配置为感测输入差分信号的共模电压的共模电压传感器，复制电路被配置为产生在第一和第二和第二至少一个处跟踪直流（DC）电压的复制电压 第二输入和比较器，被配置为将感测的共模电压与复制电压进行比较，并且基于比较来调整输入到差分公共栅放大器的第一偏置电压，其中DC电压取决于第一偏置电压 。

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