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公开(公告)号：US08102194B2
公开(公告)日：2012-01-24
申请号：US12860302
申请日：2010-08-20
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , H02M2003/077 , H03L5/00
摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。
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公开(公告)号：US07994845B2
公开(公告)日：2011-08-09
申请号：US12778960
申请日：2010-05-12
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译： 开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。 电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。 提供负电荷泵和正电荷泵实施例。 充电电路利用不重叠的宽和窄时钟信号来产生多个门控信号。 泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。 可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。
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43.发明申请公开(公告)号：US20080225615A1
公开(公告)日：2008-09-18
申请号：US12128526
申请日：2008-05-28
IPC分类号： G11C29/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译： 用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。 脉冲发生器耦合到待测量的存储单元连接到的位线。 因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。 在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。 或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。 脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。 读取电流是电流之间的差异。
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44.发明申请Test Structure for Characterizing Multi-Port Static Random Access Memory and Register File Arrays 有权用于表征多端口静态随机存取存储器和寄存器文件数组的测试结构公开(公告)号：US20080155362A1
公开(公告)日：2008-06-26
申请号：US11552158
申请日：2006-10-24
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。
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公开(公告)号：US20080122490A1
公开(公告)日：2008-05-29
申请号：US11563888
申请日：2006-11-28
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译： 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。
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公开(公告)号：US20080101522A1
公开(公告)日：2008-05-01
申请号：US11554666
申请日：2006-10-31
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译： 可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。 时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。 延迟控制信号反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。 全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。 扫描时钟前馈电路接收本地时钟并产生扫描时钟。 数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。 以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。
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公开(公告)号：US07276932B2
公开(公告)日：2007-10-02
申请号：US10926597
申请日：2004-08-26
申请人： Jente B. Kuang , Jethro C. Law , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jethro C. Law , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K19/23
CPC分类号： H03K19/0016
摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要翻译： 虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。 每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。 在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。 控制信号在单元边界被锁存或响应于时钟信号锁存。
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公开(公告)号：US06980018B2
公开(公告)日：2005-12-27
申请号：US10835501
申请日：2004-04-29
申请人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/003 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/00361
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译： 具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。 第一个逻辑路径由小型设备组成，并配置为提供缓冲区的逻辑功能，无需驱动大负载。 第二和第三逻辑路径具有直到最后一个反相级的第一逻辑路径的逻辑功能。 每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。 第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。 当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。 缓冲器可以是逆变器，非逆变器，或提供多输入逻辑功能。
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公开(公告)号：US6160292A
公开(公告)日：2000-12-12
申请号：US63823
申请日：1998-04-22
IPC分类号： G11C16/08 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： G11C16/08 , H01L27/1203
摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.
摘要翻译： 根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。 在本发明的优选实施例中，提供了一种脉冲放电电路。 这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。 如上所述，一旦累积的电荷已经耗散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。 利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。 或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。 这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。 利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。 各个器件的整体体电阻对器件的电位影响最小。
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公开(公告)号：US6151200A
公开(公告)日：2000-11-21
申请号：US452934
申请日：1999-12-02
CPC分类号： H02H9/046
摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.
摘要翻译： 通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。 当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。
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