公开(公告)号：US07212445B2

公开(公告)日：2007-05-01

申请号：US10678918

申请日：2003-10-02

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/26

摘要： A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

摘要翻译： 用于减少源极偏置的方法通过具有用于多遍感测的特征和技术的读/写电路来实现。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。 以这种方式，关闭操作不会影响感测操作。 在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。 在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

公开(公告)号：US20100182831A1

公开(公告)日：2010-07-22

申请号：US12749292

申请日：2010-03-29

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/02 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C8/08 ,  G11C8/10 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454

摘要： A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.

摘要翻译： 存储器件及其方法允许并行地编程和感测多个存储器单元，以便最小化由相邻单元的场耦合引起的误差并提高性能。 存储器件和方法具有通过相同字线链接的多个存储器单元，并且读/写电路以连续的方式耦合到每个存储器单元。 因此，存储器单元及其邻居被编程在一起，并且在编程和后续读取期间，每个存储单元相对于其邻居的现场环境变化较小。 与传统架构和偶数列上的单元格独立于奇数列中的单元进行编程的方法相比，这提高了性能并减少了从相邻单元的字段耦合引起的错误。

公开(公告)号：US07551484B2

公开(公告)日：2009-06-23

申请号：US11620946

申请日：2007-01-08

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C2207/065

摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In this way, sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells.

摘要翻译： 源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。 在感测期间，存储器单元的控制栅极电压被跨过电阻的电压降错误地偏置。 当通过接地回路的电流减小时，该误差被最小化。 用于减少源极偏置的方法通过具有用于多遍感测的特征和技术的读/写电路来实现。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 以这种方式，随后的通过中的感测将受到源极偏置的影响较小，因为通过消除来自较高电流单元的贡献，电流的总量显着减小。

公开(公告)号：US07508721B2

公开(公告)日：2009-03-24

申请号：US11566583

申请日：2006-12-04

申请人： Yan Li ,  Raul-Adrian Cernea

发明人： Yan Li ,  Raul-Adrian Cernea

IPC分类号： G11C7/10

CPC分类号： G11C16/3468

摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

摘要翻译： 非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。 示例性实施例使用快速通过写入技术，其中使用单个编程遍，但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时，选择的存储器单元的偏置被改变为慢编程 细胞。 本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器，该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元，以便在该较低级别存储验证结果。

公开(公告)号：US20080043526A1

公开(公告)日：2008-02-21

申请号：US11923126

申请日：2007-10-24

申请人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

发明人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/28 ,  G11C16/3418

摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

摘要翻译： 本发明提供了一种具有多个擦除单元或块的非易失性存储器，其中每个块被分成多个部分，共享相同的字线以保存在行解码器区域上，但可独立地读取或编程。 一个示例性实施例是具有NAND架构的闪存EEPROM存储器，其具有由左半部分和右半部分组成的块，其中每个部分将容纳512字节数据的一个或多个标准页面（数据传送单元）大小。 在示例性实施例中，块的左侧和右侧部分各自具有分离的源极线，以及分离的源极和漏极选择线组。 在左侧的编程或读取期间，作为示例，右侧可以被偏置以产生信道增强以减少数据干扰。 在另一组实施例中，这些部件可以具有单独的井结构。

公开(公告)号：US07170802B2

公开(公告)日：2007-01-30

申请号：US10751097

申请日：2003-12-31

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C29/00

CPC分类号： G11C7/1036 ,  G11C29/848

摘要： A non-volatile memory wherein bad columns in the array of memory cells can be removed. Substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. The bad column can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.

摘要翻译： 可以去除存储器单元阵列中的不良列的非易失性存储器。 替换冗余列可以替换已删除的列。 这些处理都以外部透明的方式在存储器上执行，因此不需要由附加存储器的主机或控制器在外部进行管理。 内存中可以维护坏列。 上电时，不良列的列表用于对不良列进行融合。 内存还可能包含一些可用于替换不良列的冗余列。

公开(公告)号：US07158421B2

公开(公告)日：2007-01-02

申请号：US11097517

申请日：2005-04-01

申请人： Yan Li ,  Raul-Adrian Cernea

发明人： Yan Li ,  Raul-Adrian Cernea

IPC分类号： G11C7/10

CPC分类号： G11C16/3468

摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

摘要翻译： 非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。 示例性实施例使用快速通过写入技术，其中使用单个编程遍，但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时，选择的存储器单元的偏置被改变为慢编程 细胞。 本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器，该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元，以便在该较低级别存储验证结果。

公开(公告)号：US20060092683A1

公开(公告)日：2006-05-04

申请号：US11298104

申请日：2005-12-09

申请人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

发明人： Yan Li ,  Jian Chen ,  Raul-Adrian Cernea

IPC分类号： G11C17/00

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/28 ,  G11C16/3418

摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

公开(公告)号：US07023736B2

公开(公告)日：2006-04-04

申请号：US10665828

申请日：2003-09-17

申请人： Raul-Adrian Cernea ,  Yan Li

发明人： Raul-Adrian Cernea ,  Yan Li

IPC分类号： G11C16/06

CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C2207/065

摘要： A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

摘要翻译： 用于减少源极偏置的方法通过具有用于多通感测的特征和技术的读/写电路来实现。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。 以这种方式，关闭操作不会影响感测操作。 在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。 在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

公开(公告)号：US06781877B2

公开(公告)日：2004-08-24

申请号：US10237426

申请日：2002-09-06

申请人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

发明人： Raul-Adrian Cernea ,  Khandker N. Quader ,  Yan Li ,  Jian Chen ,  Yupin Fong

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

摘要翻译： 考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。 第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程 第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。 这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。