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201 条记录 (耗时 0.052 秒)

    Method and apparatus for operating a storage device
    45.
    发明授权
    Method and apparatus for operating a storage device 失效
    用于操作存储设备的方法和设备

    公开(公告)号：US08587892B2

    公开(公告)日：2013-11-19

    申请号：US13575508

    申请日：2011-01-27

    申请人： Evangelos S. Eleftheriou ,  Walter Haeberle ,  Jens Jelitto ,  Angeliki Pantazi

    发明人： Evangelos S. Eleftheriou ,  Walter Haeberle ,  Jens Jelitto ,  Angeliki Pantazi

    IPC分类号： G11B5/584

    CPC分类号： G11B5/584

    摘要： Method for operating a storage device with a tape and a head wherein the head comprises a first and a second read element. Each read element is operable to detect servo-pattern of a particular servo band. The first and the second read element are arranged such that the tape at first passes one of both read elements and subsequently passes the other of both read elements when the tape moves in a predetermined longitudinal direction. A tape transport direction of the tape along the longitudinal direction is determined. The first read element is selected dependent on the determined tape transport direction, when the determined tape transport direction represents a direction where the tape at first passes the first read element and subsequently the second read element. Otherwise the second read element is selected. A position error signal is determined dependent on the selected read element.

    摘要翻译： 用于操作具有带和头的存储设备的方法，其中所述头部包括第一和第二读取元件。 每个读取元件可操作以检测特定伺服带的伺服图案。 第一和第二读取元件被布置成使得当磁带沿预定的纵向方向移动时，磁带首先通过两个读取元件中的一个并随后通过两个读取元件中的另一个元件。 确定带沿着纵向的带传送方向。 当所确定的磁带传送方向表示磁带首先通过第一读取单元的方向和随后的第二读取单元的方向时，第一读取单元根据确定的磁带传送方向来选择。 否则选择第二个读取元素。 取决于所选择的读取元素来确定位置误差信号。

    PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL
    46.
    发明申请
    PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL 有权
    编程至少一个多级相变记忆细胞

    公开(公告)号：US20130021845A1

    公开(公告)日：2013-01-24

    申请号：US13638311

    申请日：2011-03-23

    申请人： Evangelos S. Eleftheriou ,  Angeliki Pantazi ,  Nikolaos Papandreou ,  Haris Pozidis ,  Abu Sebastian

    发明人： Evangelos S. Eleftheriou ,  Angeliki Pantazi ,  Nikolaos Papandreou ,  Haris Pozidis ,  Abu Sebastian

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0097 ,  G11C2013/0078

    摘要： A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

    摘要翻译： 提供了一种方法，其包括通过流向PCM单元的至少一个电流脉冲对PCM单元进行编程以具有相应的确定单元状态的步骤，所述相应的确定单元状态至少由相应的确定电阻水平限定，步骤 通过相应的位线脉冲和相应的字线脉冲来控制所述各个电流脉冲，以及根据PCM单元的实际电阻值来控制所述各个位线脉冲和所述各个字线脉冲的步骤，以及相应的参考电阻值被定义为 确定阻力位。

    REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS
    47.
    发明申请
    REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS 有权
    在基于闪存的存储器系统中减少访问内容

    公开(公告)号：US20120297128A1

    公开(公告)日：2012-11-22

    申请号：US13563947

    申请日：2012-08-01

    申请人： Evangelos S. Eleftheriou ,  Robert Haas ,  Peter Mueller ,  Roman A. Pletka

    发明人： Evangelos S. Eleftheriou ,  Robert Haas ,  Peter Mueller ,  Roman A. Pletka

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7208

    摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.

    摘要翻译： 示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择处于空闲状态的芯片条带，其中芯片条带包括 多个页面，将所述条纹设置为写入状态，为所述多个通道中的每一个设置所述多个通道中的每一个中的写入队列头部，将所述写入队列头部设置到所述第一自由页面中的第一自由页面 属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，产生页写入，并响应于页写，增加写队列头，并将片段条设置为on 线状态当它满了。

    Data Management in Solid State Storage Devices
    48.
    发明申请
    Data Management in Solid State Storage Devices 有权
    固态存储设备中的数据管理

    公开(公告)号：US20120266050A1

    公开(公告)日：2012-10-18

    申请号：US13516053

    申请日：2010-12-16

    申请人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  llias Iliadis

    发明人： Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  llias Iliadis

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/108 ,  G06F11/1008 ,  G06F11/1068 ,  H03M13/05

    摘要： A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory, An indication of validity of data stored in each data write location is also maintained, Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data.

    摘要翻译： 提供了一种用于控制固态存储装置的机构，其中固态存储器包括每个包括多个数据写入位置的可擦除块。 输入数据被存储在连续的数据写入位置组中，每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。 输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。 指示固态存储器中的输入数据的位置的元数据被保持在存储器中，还保持存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，有效的输入数据从该或每个 该组在该块中包含写入位置。 然后将恢复的数据重新存储为新的输入数据。

    REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS
    50.
    发明申请
    REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS 有权
    在基于闪存的存储器系统中减少访问内容

    公开(公告)号：US20110145475A1

    公开(公告)日：2011-06-16

    申请号：US12637897

    申请日：2009-12-15

    申请人： Evangelos S. Eleftheriou ,  Robert Haas ,  Peter Mueller ,  Roman A. Pletka

    发明人： Evangelos S. Eleftheriou ,  Robert Haas ,  Peter Mueller ,  Roman A. Pletka

    IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7208

    摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.

    摘要翻译： 示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择处于空闲状态的芯片条带，其中芯片条带包括 多个页面，将所述条纹设置为写入状态，为所述多个通道中的每一个设置所述多个通道中的每一个中的写入队列头部，将所述写入队列头部设置到所述第一自由页面中的第一自由页面 属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，产生页写入，并响应于页写，增加写队列头，并将片段条设置为on 线状态当它满了。