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公开(公告)号：US4873878A
公开(公告)日：1989-10-17
申请号：US139293
申请日：1987-12-29
申请人： David W. Milton
发明人： David W. Milton
CPC分类号： G01N33/367 , D06F95/00 , D06H3/02 , D06H3/16
摘要： An apparatus for inspecting and hangering laundered pairs of pants comprises an inspection station, a hangering station and a take-away device. The inspection station includes a pants gripper which supports a pair of pants at the waist with the legs in an extended position to permit simultaneous visual and touch inspection of the pants, after which the pant legs are folded along their creases on a folding table. Hangers are delivered one at a time to a hanger catch plate at one end of the folding table which supports the hangers slightly beneath the plane of the tabletop. The pant legs are slid along the folding table and partially draped over the end of the table and the bottom wire of the hanger supported on the hanger catch plate. A take-away device contacts the hook portion of the hanger and lifts it upwardly, carrying the pants therewith, and then discharges the hangered pants onto a take-away rail for movement to another station for further processing.
摘要翻译： 用于检查和悬挂洗衣裤的裤子的装置包括检查站，悬挂站和取出装置。 检查站包括裤子夹持器，其在腰部支撑一条裤子，腿部处于延伸位置，以允许同时对裤子进行视觉和触摸检查，之后将裤腿沿着折痕折叠在折叠桌上。 衣架一次送到折叠桌的一端的衣架扣板，其支撑在桌面平面下方的衣架。 裤腿沿着折叠台滑动，并部分地覆盖在桌子的端部上，并且衣架的底部线材支撑在衣架卡扣板上。 取出装置接触衣架的钩部并将其向上提起，携带裤子，然后将悬挂的裤子排出到取出轨道上，以便移动到另一站以进一步处理。
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42.发明授权Method and system of communicating between peer processors in SoC environment 有权在SoC环境中对等处理器之间进行通信的方法和系统公开(公告)号：US09367493B2
公开(公告)日：2016-06-14
申请号：US11275091
申请日：2005-12-09
IPC分类号： G06F15/173 , G06F13/24 , G06F15/17
摘要： A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.
摘要翻译： 一种方法和系统包括将数据从第一处理器传送到直接连接到至少第二处理器的中断控制的至少一个脉冲发生器。 数据传输绕过内存。 该方法还包括由至少第二处理器直接从至少一个脉冲发生器读取传送的数据。
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公开(公告)号：US08736340B2
公开(公告)日：2014-05-27
申请号：US13534090
申请日：2012-06-27
申请人： David W. Milton
发明人： David W. Milton
摘要： Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal. In any case, a deskewer, which comprises a pair of single-ended latches and either multiplexer(s) or logic gates, processes the first differential clock signal, the single-ended clock signal, and the control signal(s) in order to output a second differential clock signal that is different from the first differential clock signal in terms of delay and, optionally, frequency, but synchronously linked to it.
摘要翻译： 公开了一种差分时钟信号发生器，其使用差分和非差分分量的组合来处理第一差分时钟信号，以产生第二差分时钟信号。 特别地，第一差分时钟信号被转换为单端时钟信号，其由有限状态机使用以产生两个单端控制信号，或由波形发生器用于产生单端波形控制信号。 在任何情况下，包括一对单端锁存器和多路复用器或逻辑门的电力负载器处理第一差分时钟信号，单端时钟信号和控制信号，以便 在延迟和可选地频率上输出不同于第一差分时钟信号的第二差分时钟信号，但是与其同步地相关联。
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公开(公告)号：US07711534B2
公开(公告)日：2010-05-04
申请号：US11275093
申请日：2005-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/3688
摘要： A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.
摘要翻译： 一种方法和系统包括提取在设计上运行离散测试用例或相关测试用例的集合所需的资源。 该方法和系统还包括基于所提取的资源构建仿真模型，并且仅使用所提取的资源（不包括整个设计）来执行仿真模型，以测试由离散测试用例或集合表示的特定功能或相关联的功能组 的相关测试用例进行设计验证，并将仿真结果与测试计划相关联。
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45.发明授权Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor 失效有效验证包括嵌入式处理器在内的片上系统集成电路设计的方法公开(公告)号：US06427224B1
公开(公告)日：2002-07-30
申请号：US09494564
申请日：2000-01-31
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. The partitioning of the verification software as described above allows for a “split-domain” mode of verification in which only the low-level code is executed by a simulated processor model, while the rest of the code executes externally to the simulator. Because most of the verification software executes externally to the simulator while only the low-level code executes on the simulated processor, the overhead of performing the high-level functions is removed from the simulator. As a result, faster verification is enabled.
摘要翻译： 一种使用验证软件来测试包括嵌入式处理器在内的片上系统（SOC）设计的方法。 验证软件用于生成和应用测试用例，以刺激模拟中的SOC设计; 观察结果并用于对设计进行设计。 包括嵌入式处理器的SOC设计的验证通常非常慢。 为了在这种情况下提供加速验证模式，在本发明的方法中，验证软件被分为更高级别的控制代码和较低级别的设备驱动程序代码。 上级代码执行决策，测试初始化，测试随机化，多任务处理以及测试结果与预期结果的比较等功能。 低级代码接口与核心正在被模拟，以便在硬件级别的操作上应用上层代码生成的测试用例。 如上所述的验证软件的划分允许“分割域”验证模式，其中只有低级代码由模拟处理器模型执行，而其余代码在模拟器外部执行。 因为大多数验证软件在模拟器外部执行，而仅在模拟处理器上执行低级代码，所以执行高级功能的开销从模拟器中移除。 因此，启用更快的验证。
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公开(公告)号：US08140314B2
公开(公告)日：2012-03-20
申请号：US12228587
申请日：2008-08-14
申请人： Robert J. Devins , David W. Milton
发明人： Robert J. Devins , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
摘要翻译： 来自总线功能模型和二进制收敛算法的采样计数反馈是为加速器或硬件辅助模拟器生成最佳采样值。 模拟器包括总线功能模型和驱动程序。 软件可读寄存器维持在总线功能模型上执行交易的模拟器提供的多个样本的计数。 对于每个支持的总线功能模型，维护从总线功能模型检索的样本计数和给定硬件辅助仿真器的最后一个采样值，并应用二进制收敛算法，以根据给予硬件辅助的最后一个采样值来生成采样值 模拟器和给定总线功能模型用于交易的最后一个实际采样值。
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47.发明授权Method and system of coherent design verification of inter-cluster interactions 有权集群间相互作用的连贯设计验证方法和系统公开(公告)号：US07849362B2
公开(公告)日：2010-12-07
申请号：US11275092
申请日：2005-12-09
IPC分类号： G06F11/00
CPC分类号： G06F11/263 , G06F11/261
摘要： A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.
摘要翻译： 一种方法和系统包括创建依赖于已知序列的测试用例，并且在始发处理器上执行测试用例，直到到达已知点。 该方法还包括在不同的处理器上执行测试用例以执行动作，并通知始发处理器已采取动作。 该动作被验证为与始发处理器一起发生。
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48.发明申请公开(公告)号：US20100194459A1
公开(公告)日：2010-08-05
申请号：US12759015
申请日：2010-04-13
申请人： David W. Milton
发明人： David W. Milton
摘要： Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.
摘要翻译： 公开了一种电路，被配置为当希望在时钟域之间同时移动信号时，将来自不同异步时钟域的一个时钟域接收的多个信号同步。 在电路中，多个基本相同的流水线信号路径接收数字输入信号。 XOR门与每个信号路径相关联。 每个XOR门监视给定信号路径中的活动并且直接或间接地控制（取决于实施例），在另一个信号路径中提高信号处理，以确保如果有必要，在电路输出节点处的输出信号是 同步 在双信号路径实施例中，每当在另一个信号路径内检测到转换的数字信号时，触发一个信号路径中的信号处理的提前。 无论何时在至少一个信号路径上检测到转换数字信号，在所有信号路径中触发信号处理的n信号通路。
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公开(公告)号：US20080312896A1
公开(公告)日：2008-12-18
申请号：US12228587
申请日：2008-08-14
申请人： Robert J. Devins , David W. Milton
发明人： Robert J. Devins , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
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公开(公告)号：US20080222583A1
公开(公告)日：2008-09-11
申请号：US11930820
申请日：2007-10-31
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译： 核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。 通常，标准化模型提供比所需更多的功能。 可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。 本发明提供了一种有效和经济的替代方案。 经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。 因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。
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