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61 条记录 (耗时 0.053 秒)

    Automatic misalignment balancing scheme for multi-patterning technology
    42.
    发明授权
    Automatic misalignment balancing scheme for multi-patterning technology 有权
    多图案化技术的自动对准平衡方案

    公开(公告)号：US08709684B2

    公开(公告)日：2014-04-29

    申请号：US13562436

    申请日：2012-07-31

    申请人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

    发明人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

    IPC分类号： G03F1/68

    CPC分类号： G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

    摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

    摘要翻译： 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

    Circuit and method for generating clock signal
    43.
    发明授权
    Circuit and method for generating clock signal 有权
    用于产生时钟信号的电路和方法

    公开(公告)号：US08705308B2

    公开(公告)日：2014-04-22

    申请号：US13737624

    申请日：2013-01-09

    申请人： Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern

    发明人： Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern

    IPC分类号： G11C7/00

    CPC分类号： G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

    摘要： A circuit includes a comparator, a first circuit, and a second circuit. The comparator includes a first input node, a second input node, and an output node. The first circuit is configured to generate a temperature-dependent reference current at the second input node of the comparator. The second circuit is coupled with the second input node of the comparator. The second circuit is configured to increase a voltage level at the second input node of the comparator in response to the temperature-dependent reference current when a signal at the output node of the comparator indicates a first comparison result, and decrease the voltage level at the second input node of the comparator when the signal at the output node of the comparator indicates a second comparison result.

    摘要翻译： 电路包括比较器，第一电路和第二电路。 比较器包括第一输入节点，第二输入节点和输出节点。 第一电路被配置为在比较器的第二输入节点处产生与温度相关的参考电流。 第二电路与比较器的第二输入节点耦合。 第二电路被配置为当比较器的输出节点处的信号指示第一比较结果时，响应于温度相关的参考电流来增加比较器的第二输入节点处的电压电平，并且降低电压电平 当比较器的输出节点处的信号指示第二比较结果时，比较器的第二输入节点。

    Phase locked loop with charge pump
    46.
    发明授权
    Phase locked loop with charge pump 有权
    带电荷泵的锁相环

    公开(公告)号：US08368437B2

    公开(公告)日：2013-02-05

    申请号：US13039095

    申请日：2011-03-02

    申请人： Ming-Chieh Huang ,  Chih-Chang Lin ,  Tao Wen Chung ,  Chan-Hong Chern

    发明人： Ming-Chieh Huang ,  Chih-Chang Lin ,  Tao Wen Chung ,  Chan-Hong Chern

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0896 ,  H03L7/089 ,  H03L7/0893

    摘要： A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.

    摘要翻译： 锁相环（PLL）包括被配置为提供输出信号的压控振荡器（VCO）。 相位频率检测器（PFD）被配置为接收参考频率信号并提供第一控制信号。 第一电荷泵被配置为接收第一控制信号并提供第一电压信号以便控制VCO。 第二电荷泵被配置为接收第一控制信号并提供第二电压信号。 比较器被配置为接收参考电压信号，以比较参考电压信号和第二电压信号，并提供第二控制信号。 PFD被配置为基于第二控制信号来调整第一控制信号的至少一个侧斜率。

    Charge pump doubler
    47.
    发明授权
    Charge pump doubler 有权
    电荷泵倍增器

    公开(公告)号：US08324960B2

    公开(公告)日：2012-12-04

    申请号：US12849503

    申请日：2010-08-03

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： H02M3/07

    摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

    摘要翻译： 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

    Integrated circuits including an LC tank circuit and operating methods thereof
    48.
    发明授权
    Integrated circuits including an LC tank circuit and operating methods thereof 有权
    包括LC电路的集成电路及其操作方法

    公开(公告)号：US08217729B2

    公开(公告)日：2012-07-10

    申请号：US12706825

    申请日：2010-02-17

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

    IPC分类号： H03B5/08

    CPC分类号： H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/099

    摘要： An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

    摘要翻译： 集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。 反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

    Automatic level control
    49.
    发明授权
    Automatic level control 有权
    自动电平控制

    公开(公告)号：US08004354B1

    公开(公告)日：2011-08-23

    申请号：US12704719

    申请日：2010-02-12

    申请人： Chiang Pu ,  Ming-Chich Huang ,  Chan-Hong Chern ,  Tien-Chun Yang

    发明人： Chiang Pu ,  Ming-Chich Huang ,  Chan-Hong Chern ,  Tien-Chun Yang

    IPC分类号： H03F1/36

    CPC分类号： G01C19/5776

    摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.

    摘要翻译： 一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。

    INTEGRATED CIRCUITS INCLUDING AN LC TANK CIRCUIT AND OPERATING METHODS THEREOF
    50.
    发明申请
    INTEGRATED CIRCUITS INCLUDING AN LC TANK CIRCUIT AND OPERATING METHODS THEREOF 有权
    集成电路，包括液相色谱电路及其操作方法

    公开(公告)号：US20110199063A1

    公开(公告)日：2011-08-18

    申请号：US12706825

    申请日：2010-02-17

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

    IPC分类号： G05F1/10

    CPC分类号： H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/099

    摘要： An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

    摘要翻译： 集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。 反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。