公开(公告)号：US20120091712A1

公开(公告)日：2012-04-19

申请号：US13145905

申请日：2010-01-22

Applicant: Ronald Hall ,  John Bradley Ball ,  Robert Allen Henry Brunet

Inventor： Ronald Hall ,  John Bradley Ball ,  Robert Allen Henry Brunet

IPC: F03D9/00 ,  H02P9/04 ,  F02B65/00

CPC classification number: F03D9/20 ,  F02B73/00 ,  F03D9/00 ,  F03D9/17 ,  F03D9/28 ,  F03D13/20 ,  F03D15/10 ,  F05B2220/70 ,  Y02E10/725

Abstract: Provided is a wind powered system for reducing energy consumption of a power source, such as an internal combustion engine or an electric motor. In one embodiment, the wind powered system comprises a wind turbine operatively connected to an internal combustion engine, for example via a direct mechanical connection, a hydrostatic drive system or a pneumatic drive system in order to reduce the amount of fuel required by the engine to operate an electricity generating means. A controller may be optionally provided to modulate the load on the wind turbine in order to maximize the extraction of available power according to local wind conditions. In another embodiment, the wind turbine is connected to an air compressor for providing a supply of air in order to offset energy consumption of a conventional compressed air system.

Abstract translation: 提供了一种用于降低诸如内燃机或电动机的动力源的能量消耗的风力发电系统。 在一个实施例中，风力发电系统包括可操作地连接到内燃机的风力涡轮机，例如通过直接机械连接，静液压驱动系统或气动驱动系统，以便将发动机所需的燃料量减少到 操作发电装置。 可以可选地提供控制器来调节风力涡轮机上的负载，以便根据当地风力条件最大限度地提取可用功率。 在另一个实施例中，风力涡轮机连接到空气压缩机以提供空气供应，以抵消传统压缩空气系统的能量消耗。

公开(公告)号：US20090285689A1

公开(公告)日：2009-11-19

申请号：US12465644

申请日：2009-05-14

Applicant: Ronald Hall ,  John Bradley Ball

Inventor： Ronald Hall ,  John Bradley Ball

IPC: F03D3/06

CPC classification number: F03D3/061 ,  F03D3/062 ,  F05B2240/213 ,  F05B2250/25 ,  Y02E10/74

Abstract: A vertical axis wind turbine comprising at least two overlapping rotor portions, each having a curved or semi-circular horizontal cross-section, each rotor portion having an outer leading edge that is angled relative to vertical from bottom to top in the direction of rotation of the wind turbine. The magnitude of the angle is in the range of from 5 to 30°. The angled leading edge improves aerodynamic performance of the wind turbine relative to the absence of the angle, particularly for turbines with three or more rotor portions.

Abstract translation: 一种垂直轴风力涡轮机，包括至少两个重叠的转子部分，每个转子部分具有弯曲或半圆形水平横截面，每个转子部分具有外侧前缘，该外部前缘相对于从底部到顶部在垂直方向 风力发电机组。 角度的大小在5至30°的范围内。 倾斜的前缘提高了风力涡轮机相对于不存在角度的空气动力性能，特别是对于具有三个或更多个转子部分的涡轮。

公开(公告)号：US20090113191A1

公开(公告)日：2009-04-30

申请号：US11923709

申请日：2007-10-25

Applicant: Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/30

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

Abstract translation: 一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 指令在循环周期长度存储在修改后的指令缓冲区中。 处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

公开(公告)号：US20090077352A1

公开(公告)日：2009-03-19

申请号：US12277376

申请日：2008-11-25

Applicant: Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

Inventor： Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

Abstract: A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.

Abstract translation: 一种用于改善按顺序处理器的性能的方法，系统和处理器。 处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。 备用管道可以存储发给正常管道的指令的副本。 执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。 通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。 结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

公开(公告)号：US20090043997A1

公开(公告)日：2009-02-12

申请号：US12250285

申请日：2008-10-13

Applicant: Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

Inventor： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

IPC: G06F7/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

Abstract: Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

Abstract translation: 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

公开(公告)号：US07475232B2

公开(公告)日：2009-01-06

申请号：US11184349

申请日：2005-07-19

Applicant: Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

Inventor： Christopher Michael Abernathy ,  Jonathan James Dement ,  Ronald Hall ,  Albert James Van Norstrand

IPC: G06F9/00

CPC classification number: G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

Abstract: A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.

Abstract translation: 一种用于改善按顺序处理器的性能的方法，系统和处理器。 处理器可以包括具有包括备用流水线和常规流水线的执行流水线的执行单元。 备用管道可以存储发给正常管道的指令的副本。 执行流水线可以包括逻辑，用于在刷新比正常流水线中检测到的异常之后的指令更新时允许指令从备用流水线流向正常流水线。 通过维护发布到常规流水线的指令的备份副本，可能不需要从单独的执行流程中刷新指令并重新获取。 结果，可以将执行单元的结果完成到设计状态，从而使完成点在不同执行流水线之间变化。

公开(公告)号：US20080229078A1

公开(公告)日：2008-09-18

申请号：US12130736

申请日：2008-05-30

Applicant: Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

Inventor： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

IPC: G06F9/30

CPC classification number: G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

Abstract: Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

Abstract translation: 介绍了处理器设计中的动态电源管理。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。

公开(公告)号：US07328330B2

公开(公告)日：2008-02-05

申请号：US11204413

申请日：2005-08-16

Applicant: Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  David Shippy

Inventor： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  David Shippy

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3885 ,  G06F9/3887

Abstract: A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions to the GP Unit and SIMD instructions to an SIMD issue queue. In the SIMD issue queue the Instruction Unit checks the SIMD instructions for dependencies and resolves these dependencies. Then the SIMD issue queue dispatches the SIMD instructions to the SIMD Unit. Accordingly, dependencies involving SIMD instructions do not affect GP instructions because the SIMD dependencies are checked and resolved independently.

Abstract translation: 提供了一种用于管理处理器的指令流水线内的SIMD指令和GP指令的方法，装置和计算机程序产品。 SIMD指令和GP指令在指令单元内共享相同的“前端”管道。 在共享管道中，指令单元检查GP指令的依赖关系并解决这些依赖关系。 在管线内的调度点，指令单元向GP单元发送有效的GP指令，向SIMD发出队列发送SIMD指令。 在SIMD问题队列中，指令单元检查SIMD指令的依赖性并解决这些依赖关系。 然后SIMD问题队列将SIMD指令发送到SIMD单元。 因此，涉及SIMD指令的依赖关系不会影响GP指令，因为SIMD依赖性被独立地检查和解决。

公开(公告)号：US07055004B2

公开(公告)日：2006-05-30

申请号：US10655366

申请日：2003-09-04

Applicant: Jonathan James DeMent ,  Ronald Hall ,  Peichun Peter Liu ,  Thuong Quang Truong

Inventor： Jonathan James DeMent ,  Ronald Hall ,  Peichun Peter Liu ,  Thuong Quang Truong

IPC: G06F12/12

CPC classification number: G06F12/126 ,  G06F12/125 ,  G06F12/127 ,  Y10S707/99945 ,  Y10S707/99948

Abstract: The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A locking or streaming replacement strategy is employed for individual sets of the cache. A replacement management table is also provided. The replacement management table is employable for managing a replacement policy of information associated with the plurality of sets. A pseudo least recently used function is employed to determine the least recently used set of the cache, for such reasons as set replacement. An override signal line is also provided. The override signal is employable to enable an overwrite of a decision node of the binary tree. A value signal is also provided. The value signal is employable to overwrite the decision node of the binary tree.

Abstract translation: 本发明提供一种采用具有决策节点的二叉树的高速缓存访​​问系统。 提供包括多个集合的高速缓存。 缓存的单独集合采用锁定或流式替换策略。 还提供了更换管理表。 替换管理表可用于管理与多个集合相关联的信息的替换策略。 由于诸如设置替换的原因，采用伪最近最少使用的功能来确定最近使用的高速缓存集合。 还提供超驰信号线。 覆盖信号可用于实现二叉树的决策节点的覆盖。 还提供了值信号。 值信号可用于覆盖二叉树的判定节点。

公开(公告)号：US20060030269A1

公开(公告)日：2006-02-09

申请号：US11247494

申请日：2005-10-10

Applicant: Gebran Sabongi ,  Ronald Hall

Inventor： Gebran Sabongi ,  Ronald Hall

IPC: H04B15/00

CPC classification number: H04W24/00

Abstract: A headset monitoring system includes a plurality of headsets and a base station. Each headset includes a microphone, a speaker, a transceiver, and a memory device for storing an identification code, and the base station includes a transceiver, a microprocessor, a memory device, and a user interface. The base station is configured to send and receive data to and from the headsets and is further configured to identify headsets that are not functioning properly.

Abstract translation: 耳机监视系统包括多个耳机和基站。 每个耳机包括麦克风，扬声器，收发器和用于存储识别码的存储器设备，并且基站包括收发器，微处理器，存储器设备和用户接口。 基站被配置为向耳机发送数据和从耳机接收数据，并且还被配置为识别不能正常工作的耳机。