中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

78 records (took 0.019 seconds)

    SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE
    44.
    发明申请
    SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE 有权

    公开(公告)号：US20210367108A1

    公开(公告)日：2021-11-25

    申请号：US17135686

    申请日：2020-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehun Kim ,  Sungwon Ko ,  Bokyoung Kim ,  Jinhwan Kim ,  Wongoo Hur

    IPC: H01L33/38 ,  H01L33/40 ,  H01L33/64 ,  H01L33/56

    Abstract: A semiconductor light emitting device includes a substrate structure, first and second regions and a main region; a light emitting structure, first and second electrode layers, an interlayer insulating layer, and a pad electrode layer. The light emitting structure is provided on the third region. The first electrode layer is provided between the substrate structure and the light emitting structure, and has a first electrode extension that extends into the first region. The second electrode layer is provided between the first electrode layer and the light emitting structure, and has a second electrode extension that extends into the second region. The interlayer insulating layer is provided between the first and second electrode layers, and has an opening exposing a portion of the first electrode extension. The pad electrode layer is provided on the interlayer insulating layer, and is connected to the portion of the first electrode extension through the opening.

    Vertical memory devices
    45.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11158651B2

    公开(公告)日：2021-10-26

    申请号：US16773103

    申请日：2020-01-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Kwangsoo Kim ,  Taehun Kim ,  Yongseok Kim ,  Kohji Kanamori

    IPC: H01L29/792 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/02

    Abstract: A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.

    Cooking apparatus
    48.
    发明授权
    Cooking apparatus 有权

    公开(公告)号：US12219682B2

    公开(公告)日：2025-02-04

    申请号：US17150946

    申请日：2021-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiho Jeong ,  Eonjoong Kim ,  Taehun Kim ,  Inki Jeon ,  Seunggee Hong

    IPC: H05B6/64 ,  F24C7/02

    Abstract: Disclosed is a cooking apparatus including a cooking chamber and, being open in a first direction, a shelf insertable into the cooking chamber in the first direction and including a container, and a magnetron to generate a high frequency to be supplied to the shelf, wherein the shelf includes a heat generating member to generate heat by the high frequency generated from the magnetron, the container includes a first container disposed on one side in a second direction orthogonal to the first direction, a second container disposed on the other side in the second direction, and a holder to detachably support the first and second containers, the heat generating member includes a first heat generating member disposed on the first container to provide heat to the first container, and a second heat generating member disposed on the second container to provide heat to the second container.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    49.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20240413079A1

    公开(公告)日：2024-12-12

    申请号：US18629785

    申请日：2024-04-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Samki Kim ,  Nambin Kim ,  Taehun Kim

    IPC: H01L23/528 ,  H01L25/065 ,  H01L29/78 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00

    Abstract: The present disclosure relates to semiconductor devices, in which a semiconductor device includes: a plate layer, gate electrodes stacked and spaced apart from each other on the plate layer in a first direction, the gate electrodes including first gate electrodes and second gate electrodes on the first gate electrodes; a horizontal insulating layer between the first gate electrodes and the second gate electrode; first channel structures extending through the first gate electrodes in the first direction; second channel structures extending through the second gate electrodes in the first direction and electrically connected to the first channel structures, respectively; contact plugs extending through the horizontal insulating layer in the first direction and connected to the gate electrodes, respectively; dummy vertical structures extending through the horizontal insulating layer in the first direction and around the contact plugs, and a cell region insulating layer covering upper surfaces of the dummy vertical structures.

    SEMICONDUCTOR PACKAGE AND METHOD OF INSPECTING THE SEMICONDUCTOR PACKAGE
    50.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF INSPECTING THE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240395747A1

    公开(公告)日：2024-11-28

    申请号：US18638757

    申请日：2024-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaekul Lee ,  Hyungsun Jang ,  Sanguk Han ,  Taehun Kim

    IPC: H01L23/00

    Abstract: A semiconductor package may include a semiconductor chip having a first surface and a second surface opposite to the first surface and having a plurality of circuit patterns provided in the second surface, a redistribution wiring layer on the second surface of the semiconductor chip and having a plurality of redistribution wirings and a plurality of bonding pads, the redistribution wirings being electrically connected to the circuit patterns, the bonding pads electrically connected to the redistribution wirings and exposed from a lower surface, a plurality of conductive bumps on the plurality of bonding pads, respectively, and a plurality of spacers on the lower surface of the redistribution wiring layer and configured to align the plurality of conductive bumps through respective through holes of a test socket and to space the redistribution wiring layer from the test socket.

Patent Agency Ranking