公开(公告)号：US11855013B2

公开(公告)日：2023-12-26

申请号：US17834020

申请日：2022-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Ho You ,  Seongho Shin ,  Bangweon Lee

IPC: H01L23/66 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L24/20 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2924/1421

Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.

公开(公告)号：US20180315698A1

公开(公告)日：2018-11-01

申请号：US16029030

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/60

CPC classification number: H01L23/49838 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US10032706B2

公开(公告)日：2018-07-24

申请号：US15236868

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/60 ,  H01L23/29

CPC classification number: H01L23/49838 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US09520387B2

公开(公告)日：2016-12-13

申请号：US14504972

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

IPC: H01L21/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Abstract translation: 提供堆叠的包装结构。 堆叠封装结构包括：堆叠封装，包括下半导体封装，设置在下半导体封装上并与下半导体封装隔开预定距离的上半导体封装;电连接下半导体封装和 上部半导体封装，同时支撑它们之间的空间，以及绝缘层，其至少设置在所述封装间连接部分的外部并填充所述下部半导体封装和所述上部半导体封装之间的空间，以及围绕所述下部半导体封装的横向和顶部表面的电磁屏蔽层 堆叠包装。

公开(公告)号：US11380635B2

公开(公告)日：2022-07-05

申请号：US17121898

申请日：2020-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Ho You ,  Seongho Shin ,  Bangweon Lee

IPC: H01L23/66 ,  H01L23/00

Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.

公开(公告)号：US10256181B2

公开(公告)日：2019-04-09

申请号：US16029030

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/60 ,  H01L23/29

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US09030838B2

公开(公告)日：2015-05-12

申请号：US14147114

申请日：2014-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Ho You ,  Heeseok Lee ,  Chiyoung Lee ,  Yun-Hee Lee

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H05K1/11 ,  H01L23/13 ,  H01L23/498

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/48227 ,  H01L2225/107 ,  H01L2924/1515 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/18 ,  H05K1/181 ,  Y02P70/611

Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract translation: 提供了封装基板和半导体封装。 封装基板包括具有上表面和与上表面相对的下表面的主体，附接到下表面的多个外部端子，以及形成在下表面的多个外部区域中的多个凹槽 端子未连接。 半导体封装包括封装衬底，安装在半导体衬底的上表面上的半导体芯片，以及提供安装有封装衬底的区域的板，并且安装有与多个沟槽垂直对准的多个安装元件 并插入到多个槽中。

公开(公告)号：US11482509B2

公开(公告)日：2022-10-25

申请号：US16906051

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Ho You ,  Kyung Suk Oh ,  Sunkyoung Seo

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L25/00

Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.