公开(公告)号：US11127728B2

公开(公告)日：2021-09-21

申请号：US16848137

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: G11C5/04 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L23/48

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

公开(公告)号：US11024648B2

公开(公告)日：2021-06-01

申请号：US16743436

申请日：2020-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Yanli Zhang ,  Seung-Yeul Yang ,  Fei Zhou

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A ferroelectric memory device includes a semiconductor channel, a gate electrode, and a ferroelectric memory element located between the semiconductor channel and the gate electrode. The ferroelectric memory element includes at least one ferroelectric material portion and at least one antiferroelectric material portion.

公开(公告)号：US10797061B2

公开(公告)日：2020-10-06

申请号：US16221942

申请日：2018-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Toshihiro Iizuka ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou ,  Srikanth Ranganathan

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L29/08 ,  H01L29/10 ,  H01L21/324 ,  H01L27/11565 ,  H01L21/8239 ,  H01L21/8234 ,  H01L27/11573 ,  H01L27/11529

Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.

公开(公告)号：US10790300B2

公开(公告)日：2020-09-29

申请号：US16290277

申请日：2019-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Rahul Sharangpani

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.

公开(公告)号：US20200243500A1

公开(公告)日：2020-07-30

申请号：US16848137

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: H01L25/18 ,  G11C16/26 ,  H01L25/00 ,  H01L23/00 ,  G11C16/08 ,  H01L23/48 ,  G11C16/30 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/24

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

公开(公告)号：US10665581B1

公开(公告)日：2020-05-26

申请号：US16255413

申请日：2019-01-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: G11C5/04 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L23/48

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

公开(公告)号：US12219776B2

公开(公告)日：2025-02-04

申请号：US17578199

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Kartik Sondhi

IPC: H10B51/20 ,  H01L23/48 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US11569260B2

公开(公告)日：2023-01-31

申请号：US17001003

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Rahul Sharangpani

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519

Abstract: A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.

公开(公告)号：US11545506B2

公开(公告)日：2023-01-03

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati Prasad ,  Joyeeta Nag ,  Seung-Yeul Yang ,  Adarsh Rajashekhar ,  Raghuveer S. Makala

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US11450687B2

公开(公告)日：2022-09-20

申请号：US17122360

申请日：2020-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Tirukkonda ,  Ramy Nashed Bassely Said ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11585 ,  H01L27/11578

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.