公开(公告)号：US10797061B2

公开(公告)日：2020-10-06

申请号：US16221942

申请日：2018-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akio Nishida ,  Toshihiro Iizuka ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou ,  Srikanth Ranganathan

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L29/08 ,  H01L29/10 ,  H01L21/324 ,  H01L27/11565 ,  H01L21/8239 ,  H01L21/8234 ,  H01L27/11573 ,  H01L27/11529

Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.

公开(公告)号：US10853244B2

公开(公告)日：2020-12-01

申请号：US15604994

申请日：2017-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Christopher Petti ,  Srikanth Ranganathan

IPC: G06F12/06 ,  G11C13/00 ,  C12N15/11

Abstract: A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.

公开(公告)号：US09842857B2

公开(公告)日：2017-12-12

申请号：US15440365

申请日：2017-02-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Sateesh Koka ,  Raghuveer S. Makala ,  Srikanth Ranganathan ,  Mark Juanitas ,  Johann Alsmeier

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02321 ,  H01L21/02356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7883

Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.

公开(公告)号：US10797060B2

公开(公告)日：2020-10-06

申请号：US16221894

申请日：2018-12-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Fei Zhou ,  Srikanth Ranganathan ,  Akio Nishida ,  Toshihiro Iizuka

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L21/8239 ,  H01L27/1157 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10

Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.

公开(公告)号：US10109680B1

公开(公告)日：2018-10-23

申请号：US15622100

申请日：2017-06-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sebastian J. M. Wicklein ,  Juan P. Saenz ,  Srikanth Ranganathan ,  Ming-Che Wu ,  Tanmay Kumar

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.

公开(公告)号：US20170162597A1

公开(公告)日：2017-06-08

申请号：US15440365

申请日：2017-02-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Sateesh Koka ,  Raghuveer S. Makala ,  Srikanth Ranganathan ,  Mark Juanitas ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02321 ,  H01L21/02356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7883

Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.