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公开(公告)号：US20190371406A1
公开(公告)日：2019-12-05
申请号：US16000237
申请日：2018-06-05
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.
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公开(公告)号：US20190252030A1
公开(公告)日：2019-08-15
申请号：US15963647
申请日：2018-04-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta , Jianzhi Wu , Gerrit Jan Hemink
Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.
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公开(公告)号：US12254931B2
公开(公告)日：2025-03-18
申请号：US17845060
申请日：2022-06-21
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Deepanshu Dutta , Jiacen Guo , Takayuki Inoue , Hua-Ling Hsu
Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
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公开(公告)号：US12205657B2
公开(公告)日：2025-01-21
申请号：US17895412
申请日：2022-08-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Henry Chin , Erika Penzo , Muhammad Masuduzzaman
Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
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公开(公告)号：US20240355401A1
公开(公告)日：2024-10-24
申请号：US18346352
申请日：2023-07-03
Applicant: SanDisk Technologies LLC
Inventor： Wei Cao , Xiang Yang , Peng Zhang
CPC classification number: G11C16/3459 , G11C16/0433 , G11C16/08 , G11C16/102
Abstract: To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.
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Patent Agency Ranking
公开(公告)号：US12079496B2
公开(公告)日：2024-09-03
申请号：US17901310
申请日：2022-09-01
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Xiang Yang
IPC: G06F3/06
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0679
Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.
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公开(公告)号：US12046305B2
公开(公告)日：2024-07-23
申请号：US17665267
申请日：2022-02-04
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Abhijith Prakash
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/14 , G11C16/28 , G11C16/3404
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.
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公开(公告)号：US20240201882A1
公开(公告)日：2024-06-20
申请号：US18220707
申请日：2023-07-11
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0679
Abstract: The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on the first and second word lines, the first word line is further programmed in a second programming pass that includes a plurality of program loops with pre-charge operations. The spike pre-charge voltage is applied to the second word line during each pre-charge operation.
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公开(公告)号：US12014785B2
公开(公告)日：2024-06-18
申请号：US17511988
申请日：2021-10-27
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang
CPC classification number: G11C16/3427 , G11C16/0483
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory cells that is individually adapted for each of the plurality of groupings. The control means then applies the unique select gate voltage to the drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the drain-side select gate transistor of the selected ones of the strings during a memory operation.
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公开(公告)号：US20240194277A1
公开(公告)日：2024-06-13
申请号：US18360306
申请日：2023-07-27
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang , Yi Song , Jiahui Yuan
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/26
Abstract: Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.
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