公开(公告)号：US20150295029A1

公开(公告)日：2015-10-15

申请号：US14249882

申请日：2014-04-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume ROIG GUITART ,  Zia HOSSAIN ,  Peter MOENS ,  Gordon M. GRIVNA

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract translation: 电子设备可以包括电子部件和与电子部件区域相邻的端接区域。 在一个实施例中，终端区域可以包括将深度延伸到半导体层中的绝缘区域，其中深度小于半导体层厚度的50％。 在另一个实施例中，终端区域可以包括将第一深度延伸到半导体层中的第一绝缘区域和将第二深度延伸到半导体层中的第二绝缘区域，其中第二深度小于第一深度。 在另一方面，形成电子器件的工艺可以包括图案化半导体层以限定终止区域内的沟槽，同时为电子部件区域内的电子部件形成另一个沟槽。

公开(公告)号：US20140264523A1

公开(公告)日：2014-09-18

申请号：US14168492

申请日：2014-01-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L28/90 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66181 ,  H01L29/945

Abstract: An electronic device can include a capacitor structure. In an embodiment, the electronic device can include a buried conductive region, a semiconductor layer having a primary surface, a horizontally-oriented doped region adjacent to the primary surface, an insulating layer overlying the horizontally-oriented doped region, and a conductive electrode overlying the insulating layer. The capacitor structure can include a first capacitor electrode including a vertical conductive region electrically connected to the horizontally-oriented doped region and the buried conductive region. The capacitor structure can further include a capacitor dielectric layer and a second capacitor electrode within a trench. The capacitor structure can be spaced apart from the conductive electrode. In another embodiment, an electronic device can include a first transistor, a trench capacitor structure, and a second transistor, wherein the first transistor is coupled to the trench capacitor structure, and the second transistor does not have a corresponding trench capacitor structure.

Abstract translation: 电子设备可以包括电容器结构。 在一个实施例中，电子器件可以包括掩埋导电区域，具有主表面的半导体层，与主表面相邻的水平取向的掺杂区域，覆盖在水平取向的掺杂区域上的绝缘层，以及覆盖 绝缘层。 电容器结构可以包括第一电容器电极，其包括电连接到水平取向掺杂区域和埋入导电区域的垂直导电区域。 电容器结构还可以包括沟槽内的电容器电介质层和第二电容器电极。 电容器结构可以与导电电极间隔开。 在另一个实施例中，电子器件可以包括第一晶体管，沟槽电容器结构和第二晶体管，其中第一晶体管耦合到沟槽电容器结构，而第二晶体管不具有对应的沟槽电容器结构。

公开(公告)号：US20140145256A1

公开(公告)日：2014-05-29

申请号：US14171427

申请日：2014-02-03

Applicant: Semiconductor Components Industries, LLC

Inventor： Prasad VENKATRAMAN ,  Gordon M. GRIVNA ,  Gary H. LOECHELT

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7835

Abstract: An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.

Abstract translation: 电子器件可以包括覆盖衬底并具有主表面和厚度的半导体层，其中沟槽延伸穿过半导体层厚度的至少大约50％的深度。 电子器件还可以包括在沟槽内的导电结构，其中导电结构延伸至沟槽深度的至少约50％。 电子器件还可以进一步包括在半导体层内的垂直取向的掺杂区域，该掺杂区域与导电结构相邻并与导电结构电绝缘; 以及设置在垂直取向的掺杂区域和导电结构之间的绝缘层。 形成电子器件的过程可以包括图案化半导体层以限定延伸穿过至少大约50％的半导体层的厚度的沟槽，并且在图案化半导体层以形成沟槽之后形成垂直取向的掺杂区域。

公开(公告)号：US20140091399A1

公开(公告)日：2014-04-03

申请号：US14099214

申请日：2013-12-06

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/2815 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/10 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/6625 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

Abstract translation: 包括集成电路的电子器件可以包括掩埋导电区域和覆盖掩埋导电区域的半导体层，其中半导体层具有更靠近掩埋导电区域的主表面和相对表面。 电子器件还可以包括彼此间隔开的第一掺杂区域和第二掺杂区域，其中每个在半导体层内并且比相对表面更靠近主表面。 电子装置可以包括晶体管的载流电极。 特定晶体管的载流电极包括第一掺杂区域，并且是源极或发射极，并且电连接到掩埋导电区域。 不同晶体管的另一载流电极包括第二掺杂区，并且是漏极或集电极，并且电连接到掩埋导电区。

公开(公告)号：US20230402325A1

公开(公告)日：2023-12-14

申请号：US18453721

申请日：2023-08-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/67288 ,  H01L21/30655

Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.

公开(公告)号：US20230095014A1

公开(公告)日：2023-03-30

申请号：US18062152

申请日：2022-12-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L29/165 ,  H01L21/285 ,  H01L29/06 ,  H01L49/02

Abstract: A semiconductor device includes a work piece comprising a first material, a first side, a second side opposite to the first side, and a first coefficient of thermal expansion (first CTE). Recesses extend into the work piece from the first side and includes a pattern. A second material having a second CTE is within the recesses and is over the first material between the recesses; and A third material having a third CTE is over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.

公开(公告)号：US20220262633A1

公开(公告)日：2022-08-18

申请号：US17661890

申请日：2022-05-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Stephen ST. GERMAIN

IPC: H01L21/02 ,  H01L21/78 ,  H01L29/20 ,  H01L23/495 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

公开(公告)号：US20220020848A1

公开(公告)日：2022-01-20

申请号：US16948801

申请日：2020-10-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/20 ,  H01L25/07

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

公开(公告)号：US20210183705A1

公开(公告)日：2021-06-17

申请号：US17248751

申请日：2021-02-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/67 ,  H01L21/683 ,  H01L21/3065

Abstract: An apparatus for singulating a layer of material on a semiconductor substrate includes a chamber. The chamber is configured for supporting a semiconductor substrate attached to a carrier substrate, the semiconductor substrate can include a plurality of die formed as part of the semiconductor substrate and separated from each other by singulation lines and a layer of material disposed over a major surface of the semiconductor substrate. In some examples, the singulation lines terminate so that the layer of material extends over the singulation lines. The apparatus includes a pressure transfer vessel inside the chamber and a compression structure movably associated with the chamber. The compression structure can be configured so that the pressure transfer vessel is interposed between the semiconductor substrate and the compression structure. The compression structure and the pressure transfer vessel are adapted to apply pressure to the entire semiconductor substrate to singulate the layer of material that extends over the singulation lines.

公开(公告)号：US20210118739A1

公开(公告)日：2021-04-22

申请号：US17136319

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/67 ,  H01L21/3065

Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.