公开(公告)号：US20150295025A1

公开(公告)日：2015-10-15

申请号：US14249677

申请日：2014-04-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume ROIG GUITART ,  Zia HOSSAIN ,  Peter MOENS

IPC: H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0634 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/40 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract translation: 电子设备可以包括电子部件和与电子部件区域相邻的端接区域。 在一个实施例中，终端区域可以包括将深度延伸到半导体层中的绝缘区域，其中深度小于半导体层厚度的50％。 在另一个实施例中，终端区域可以包括将第一深度延伸到半导体层中的第一绝缘区域和将第二深度延伸到半导体层中的第二绝缘区域，其中第二深度小于第一深度。 在另一方面，形成电子器件的工艺可以包括图案化半导体层以限定终止区域内的沟槽，同时为电子部件区域内的电子部件形成另一沟槽。

公开(公告)号：US20160087033A1

公开(公告)日：2016-03-24

申请号：US14930060

申请日：2015-11-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG GUITART ,  Peter MOENS ,  Piet VANMEERBEEK

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7827

Abstract: In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.

Abstract translation: 在一个实施例中，半导体器件具有邻接低掺杂n型区域形成的超结构结构。 在低掺杂n型区域之上形成邻接超结构结构的低掺杂p型区域，并且被配置为改善Eas特性。 在低掺杂p型区域附近形成体区，并且在身体区域附近形成控制电极结构，以控制体区内的通道区域。

公开(公告)号：US20170062411A1

公开(公告)日：2017-03-02

申请号：US14843852

申请日：2015-09-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG GUITART ,  Samir MOUHOUBI ,  Filip BAUWENS

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/665 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8725

Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.

Abstract translation: 半导体器件包括限定主表面的半导体衬底。 该装置还包括第一区域，该第一区域至少包括相对于该主表面在垂直取向上延伸的第一导电类型的第一支柱。 该装置还包括第一导电类型的第二区域。 第一支柱包括比第二区域更高的掺杂浓度。 该器件还包括耦合到第二区域的肖特基接触。

公开(公告)号：US20150295029A1

公开(公告)日：2015-10-15

申请号：US14249882

申请日：2014-04-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume ROIG GUITART ,  Zia HOSSAIN ,  Peter MOENS ,  Gordon M. GRIVNA

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract translation: 电子设备可以包括电子部件和与电子部件区域相邻的端接区域。 在一个实施例中，终端区域可以包括将深度延伸到半导体层中的绝缘区域，其中深度小于半导体层厚度的50％。 在另一个实施例中，终端区域可以包括将第一深度延伸到半导体层中的第一绝缘区域和将第二深度延伸到半导体层中的第二绝缘区域，其中第二深度小于第一深度。 在另一方面，形成电子器件的工艺可以包括图案化半导体层以限定终止区域内的沟槽，同时为电子部件区域内的电子部件形成另一个沟槽。