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    HEMT DEVICES WITH REDUCED SIZE AND HIGH ALIGNMENT TOLERANCE
    1.
    发明申请
    HEMT DEVICES WITH REDUCED SIZE AND HIGH ALIGNMENT TOLERANCE 有权

    公开(公告)号：US20240395922A1

    公开(公告)日：2024-11-28

    申请号：US18796258

    申请日：2024-08-06

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter COPPENS ,  Peter MOENS ,  Joris BAELE

    IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

    Abstract: A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.

    MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES
    3.
    发明申请
    MONOLITHIC SEMICONDUCTOR DEVICE ASSEMBLIES 有权

    公开(公告)号：US20220020848A1

    公开(公告)日：2022-01-20

    申请号：US16948801

    申请日：2020-10-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

    IPC: H01L29/06 ,  H01L21/762 ,  H01L29/20 ,  H01L25/07

    Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

    ELECTRONIC DEVICE INCLUDING AN ACCESS REGION AND A PROCESS OF FORMING THE SAME
    4.
    发明申请
    ELECTRONIC DEVICE INCLUDING AN ACCESS REGION AND A PROCESS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20190371909A1

    公开(公告)日：2019-12-05

    申请号：US15997122

    申请日：2018-06-04

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Abhishek BANERJEE ,  Piet VANMEERBEEK ,  Peter MOENS ,  Marnix TACK

    IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28

    Abstract: An electronic device can include a channel layer; an access region having an aluminum content substantially uniform or increasing with distance from the channel layer; and a gate dielectric layer overlying and contacting the channel layer. A process of forming an electronic device can include providing a substrate and a channel layer of a III-V semiconductor material over the substrate; forming a masking feature over the channel layer; and forming an access region over the channel layer. In an embodiment, the channel layer can include GaN, and the access region has an aluminum content that is substantially uniform or increases with distance from the channel layer. In another embodiment, the process can include removing at least a portion the masking feature and forming a gate dielectric layer over the channel layer. A dielectric film of the masking feature or the gate dielectric layer contacts the channel layer.

    Electronic Device Including a HEMT Including a Buried Region
    7.
    发明申请
    Electronic Device Including a HEMT Including a Buried Region 审中-公开

    公开(公告)号：US20200219871A1

    公开(公告)日：2020-07-09

    申请号：US16241172

    申请日：2019-01-07

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Peter MOENS ,  Arno Stockman ,  Piet VANMEERBEEK ,  Abhishek BANERJEE ,  Frederick Johan G. DECLERCQ

    IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

    Abstract: An electronic device can include a high electron mobility transistor that includes a buried region, a channel layer overlying the buried region, a gate electrode, and a drain electrode overlying the buried region. The buried region can extend toward and does not underlie the gate electrode. In a particular aspect, the electronic device can further include a p-type semiconductor member overlying the channel layer. The gate electrode can overlie the channel layer, a p-type semiconductor member overlying the channel layer. The drain electrode can overlie and contact the buried region and the p-type semiconductor member. The p-type semiconductor member can be disposed between the gate and drain electrodes. In another embodiment, a source-side buried region may be used in addition to or in place of the buried region that is coupled to the drain electrode.

    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE
    8.
    发明申请
    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE 审中-公开

    公开(公告)号：US20190035910A1

    公开(公告)日：2019-01-31

    申请号：US15662622

    申请日：2017-07-28

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Peter MOENS ,  Abhishek BANERJEE

    IPC: H01L29/66 ,  H01L29/20 ,  H01L29/32 ,  H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324

    Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.

    SEMICONDUCTOR STRUCTURE INCLUDING A DOPED BUFFER LAYER AND A CHANNEL LAYER AND A PROCESS OF FORMING THE SAME
    10.
    发明申请
    SEMICONDUCTOR STRUCTURE INCLUDING A DOPED BUFFER LAYER AND A CHANNEL LAYER AND A PROCESS OF FORMING THE SAME 审中-公开
    包括DOPED缓冲层和通道层的半导体结构及其形成过程

    公开(公告)号：US20160126312A1

    公开(公告)日：2016-05-05

    申请号：US14867131

    申请日：2015-09-28

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Peter MOENS

    IPC: H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

    CPC classification number: H01L29/1075 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/404 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×1015 atoms/cm3.

    Abstract translation: 半导体结构可以包括衬底，覆盖衬底的高电压阻挡层，覆盖高压层的掺杂缓冲层和覆盖掺杂缓冲层的沟道层，其中掺杂缓冲层和沟道层包括 相同的化合物半导体材料，并且掺杂缓冲层具有处于第一载流子杂质浓度的载流子杂质类型，沟道缓冲层具有小于第一载流子杂质浓度的第二载流子杂质浓度的载流子杂质类型。 在一个实施例中，沟道层具有至少650nm的厚度。 在另一个实施例中，高电压阻挡包括1000nm厚且邻近掺杂缓冲层的近端区域，并且近端区域，掺杂缓冲层和沟道层中的每一个具有小于5的Fe杂质浓度 ×1015个原子/ cm3。

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