公开(公告)号：US20220084920A1

公开(公告)日：2022-03-17

申请号：US17457148

申请日：2021-12-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen ST. GERMAIN ,  Jay A. YODER ,  Dennis Lee CONNER ,  Frank Robert CERVANTES ,  Andrew Celaya

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

公开(公告)号：US20210035956A1

公开(公告)日：2021-02-04

申请号：US16678039

申请日：2019-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20190385939A1

公开(公告)日：2019-12-19

申请号：US16554980

申请日：2019-08-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen ST. GERMAIN ,  Jay A. YODER ,  Dennis Lee CONNER ,  Frank Robert CERVANTES ,  Andrew Celaya

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

公开(公告)号：US20190326202A1

公开(公告)日：2019-10-24

申请号：US16459954

申请日：2019-07-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Roger M. ARBUTHNOT ,  Stephen ST. GERMAIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56

Abstract: Various leadframe implementations may include a conductive substrate electrically coupled to a first lead where the conductive substrate includes a first elevated region and a second elevated region on a first side of the conductive substrate. The first elevated region may include a first planar surface and the second elevated region may include a second planar surface on the first side of the conductive substrate. Various implementations may include where the first planar surface of the first elevated region and the second planar surface of the second elevated region are configured to attach to a contact pad of a semiconductor die. The first planar surface may include a curved edge. The second planar surface may include a polygonal shape. The curved edge of the first planar surface may be configured to laterally align with a curved edge of the contact pad of the semiconductor die.

公开(公告)号：US20220415766A1

公开(公告)日：2022-12-29

申请号：US17929884

申请日：2022-09-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20180053712A1

公开(公告)日：2018-02-22

申请号：US15240423

申请日：2016-08-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen ST. GERMAIN ,  Dennis Lee CONNER ,  Jay A. YODER

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/84 ,  H01L2224/29191 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/92246 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715

Abstract: A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface having been etched; and one or more holes passing through said lead frame and coincident with the first and second surfaces, wherein said one or more holes are adapted to control fluid flow on said first surface.

公开(公告)号：US20170110391A1

公开(公告)日：2017-04-20

申请号：US15391960

申请日：2016-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen ST. GERMAIN ,  Roger M. ARBUTHNOT ,  Jay A. YODER ,  Dennis Lee CONNER

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.

公开(公告)号：US20230317576A1

公开(公告)日：2023-10-05

申请号：US18330133

申请日：2023-06-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen ST. GERMAIN ,  Jay A. YODER ,  Dennis Lee CONNER ,  Frank Robert CERVANTES ,  Andrew CELAYA

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L23/49861 ,  H01L23/49811 ,  H01L21/568 ,  H01L23/49562 ,  H01L23/49524 ,  H01L23/3107 ,  H01L23/49575 ,  H01L2924/181 ,  H01L2924/0002

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

公开(公告)号：US20220208637A1

公开(公告)日：2022-06-30

申请号：US17655398

申请日：2022-03-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Liangbiao CHEN ,  Yong LIU ,  Tzu-Hsuan CHENG ,  Stephen ST. GERMAIN ,  Roger ARBUTHNOT

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/373 ,  H01L23/31 ,  H01L23/00 ,  H05K7/20

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.
Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.

公开(公告)号：US20210249329A1

公开(公告)日：2021-08-12

申请号：US16784999

申请日：2020-02-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Liangbiao CHEN ,  Yong LIU ,  Tzu-Hsuan CHENG ,  Stephen ST. GERMAIN ,  Roger ARBUTHNOT

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/373 ,  H01L23/31 ,  H05K7/20 ,  H01L23/00

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.