公开(公告)号：US11296039B2

公开(公告)日：2022-04-05

申请号：US17017910

申请日：2020-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L23/00 ,  H01L29/06

Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.

公开(公告)号：US11164875B2

公开(公告)日：2021-11-02

申请号：US16803226

申请日：2020-02-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L27/108 ,  H01L27/11521 ,  H01L49/02 ,  H01L29/66 ,  H01L29/94

Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

公开(公告)号：US11081488B2

公开(公告)日：2021-08-03

申请号：US17026874

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US10818669B2

公开(公告)日：2020-10-27

申请号：US16111480

申请日：2018-08-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20190027448A1

公开(公告)日：2019-01-24

申请号：US16139370

申请日：2018-09-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L23/00 ,  H01L29/06

Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.

公开(公告)号：US10109601B2

公开(公告)日：2018-10-23

申请号：US15698882

申请日：2017-09-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: B24B37/013 ,  H01L23/00 ,  H01L29/06

Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.

公开(公告)号：US20150037966A1

公开(公告)日：2015-02-05

申请号：US14451161

申请日：2014-08-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yoann Goasduff ,  Abderrezak Marzaki

IPC: H01L21/308 ,  H01L21/266

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/3085

Abstract: At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench.

Abstract translation: 在元件中形成至少一个突出块。 突出的块然后被第一覆盖层覆盖，以形成与突出块自对准的凹脊，并且其凹面朝向突出块。 然后以与脊和突出块两者自对准的方式在脊中形成第一沟槽。 第一沟槽延伸到到达突出块的深度。 使用脊和第一沟槽蚀刻突出块作为蚀刻掩模，以在与第一沟槽自对准的突出块中形成第二沟槽。 因此，通过限定第二沟槽的突出块的第二沟槽和未蚀刻部分产生图案。

公开(公告)号：US11943931B2

公开(公告)日：2024-03-26

申请号：US17220286

申请日：2021-04-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H10B43/35 ,  G11C5/06 ,  H10B43/10

CPC classification number: H10B43/35 ,  G11C5/063 ,  H10B43/10

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US11818883B2

公开(公告)日：2023-11-14

申请号：US17540029

申请日：2021-12-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

公开(公告)号：US11640972B2

公开(公告)日：2023-05-02

申请号：US17591233

申请日：2022-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.