公开(公告)号：US10964791B2

公开(公告)日：2021-03-30

申请号：US16014496

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan Hwang ,  Heonjong Shin ,  Sunghun Jung ,  Doohyun Lee ,  Hwichan Jun ,  Hakyoon Ahn

IPC: H01L29/417 ,  H01L29/423 ,  H01L21/285 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US20180219010A1

公开(公告)日：2018-08-02

申请号：US15937093

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGHWA KIM ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.