公开(公告)号：US20090034335A1

公开(公告)日：2009-02-05

申请号：US12283721

申请日：2008-09-15

申请人： Yasuhiko Tanuma ,  Kazuhiro Kurihara

发明人： Yasuhiko Tanuma ,  Kazuhiro Kurihara

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.

摘要翻译： 半导体器件包括具有连接到本地字线的存储器单元的扇区，选择扇区的解码器，以及在擦除所选择的扇区时产生使与选择的扇区相关联的解码器中的对应的一个解码器暂时地产生的控制信号的电路 未选择 每个扇区包括一个上拉晶体管，该上拉晶体管经由相应的解码器之一经由连接扇区的全局字线对应的一个驱动本地字线之一，并且上拉晶体管由 控制信号。

公开(公告)号：US07023897B2

公开(公告)日：2006-04-04

申请号：US10020186

申请日：2001-12-18

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04J13/00 ,  H04B1/707 ,  H04B2201/70703 ,  H04J13/0077

摘要： A transmission circuit includes a baseband circuit, spreading section, multiplier, digital modulator, quadrature modulator, and antenna. The baseband circuit generates and outputs at least one transmission data constituted by first and second channel data. The spreading section spreads the transmission data with a spreading code that differs for each transmission channel. The multiplier respectively weights the amplitudes of the first and second channel data by using a combination of two gain factors determined by a transmission data rate. The digital modulator digitally modulates the first and second channel data whose amplitudes are weighted by the multiplier. The quadrature modulator quadrature-modulates the digitally modulated first and second channel data and outputs the data as a transmission signal. The antenna emits the transmission signal output from the quadrature modulator as a radio wave. The multiplier weights the amplitudes of the first and second channel data by using gain factors that keep power of the transmission signal output from the quadrature modulator constant regardless of the transmission data rate without changing the ratio of a combination of gain factors determined by the transmission data rate.

公开(公告)号：US06819591B1

公开(公告)日：2004-11-16

申请号：US10762071

申请日：2004-01-20

申请人： Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Santosh Yachareni ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Santosh Yachareni ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C16/0491

摘要： An exemplary memory sector erase method comprises the steps of pre-programming a first bit and a second bit of a plurality of core memory cells of a plurality of memory blocks of a target memory sector, pre-programming one of a third bit and a fourth bit of a first neighboring memory cell adjacent to the target memory sector, and erasing the first bit and the second bit of the plurality of core memory cells of the plurality of memory blocks. According to another embodiment, the method further comprises programming the one of the third bit and the fourth bit of the first neighboring memory cell after the erasing step.

摘要翻译： 示例性存储器扇区擦除方法包括以下步骤：对目标存储器扇区的多个存储器块的多个核心存储器单元的第一位和第二位进行预编程，预编程第三位和第四 与目标存储器扇区相邻的第一相邻存储单元的位，以及擦除多个存储块中的多个存储单元的第一位和第二位。 根据另一实施例，该方法还包括在擦除步骤之后编程第一相邻存储器单元的第三位和第四位之一。

公开(公告)号：US06791880B1

公开(公告)日：2004-09-14

申请号：US10431320

申请日：2003-05-06

申请人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

发明人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C16/349 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。

公开(公告)号：US06721370B1

公开(公告)日：2004-04-13

申请号：US09421851

申请日：1999-10-20

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： H04L2503

CPC分类号： H03F1/3247 ,  H03G3/30

摘要： A phase correction circuit for a radio communication apparatus includes a variable gain amplifier and phase correction unit. The variable gain amplifier amplifies a transmission/reception signal on the basis of a gain variably set in accordance with a gain signal. The phase correction unit has a phase characteristic opposite to that of the variable gain amplifier, corrects the phase of the transmission/reception signal on the basis of the gain signal supplied to the variable gain amplifier, and cancels a phase change of the signal caused in the variable gain amplifier.

摘要翻译： 无线电通信装置的相位校正电路包括可变增益放大器和相位校正单元。 可变增益放大器基于根据增益信号可变地设定的增益来放大发送/接收信号。 相位校正单元具有与可变增益放大器的相位特性相反的相位特性，根据提供给可变增益放大器的增益信号来校正发送/接收信号的相位，并且消除由 可变增益放大器。

公开(公告)号：US06713809B1

公开(公告)日：2004-03-30

申请号：US09809969

申请日：2001-03-16

申请人： Jusuke Ogura ,  Kazuhiro Kurihara ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

发明人： Jusuke Ogura ,  Kazuhiro Kurihara ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。

公开(公告)号：US06574139B2

公开(公告)日：2003-06-03

申请号：US10052484

申请日：2002-01-18

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method for reading at least one programmed dual bit memory cell using a plurality of programmed dual bit reference cells. The reference cells are programmed with selected parameters to compensate for changes in the memory cell. The memory cell is read and compared to data in the reference cells to determine the memory cell data. Thus, changes to the memory cell over time are accounted for by programming the reference cells using the selected parameters.

摘要翻译： 一种用于使用多个编程的双位参考单元读取至少一个编程的双位存储单元的方法。 参考单元用选定的参数进行编程，以补偿存储单元的变化。 读取存储器单元并与参考单元中的数据进行比较以确定存储单元数据。 因此，通过使用所选择的参数对参考单元进行编程来解释对存储单元随时间的变化。

公开(公告)号：US06469942B1

公开(公告)日：2002-10-22

申请号：US09920248

申请日：2001-07-31

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C16/08

摘要： System for boosting a signal for use in a memory device. The system includes a circuit for providing a boosted signal used to produce a word line signal in a memory device. The circuit includes a pre-charge stage that has an output terminal and is coupled to receive an address signal and a boost control signal. The pre-charge stage is operable to produce the boosted signal having a pre-charged level at the output terminal. The circuit also includes a boost stage that is coupled to receive the boost control signal and produce a boost activation signal at a boost stage output terminal that is coupled to the output terminal via a capacitive element. When the boost activation signal is active, the boosted signal is set to a selected boost level that is independent of supply voltage.

摘要翻译： 用于升高用于存储器件的信号的系统。 该系统包括用于提供用于在存储器件中产生字线信号的升压信号的电路。 该电路包括具有输出端并被耦合以接收地址信号和升压控制信号的预充电级。 预充电阶段可操作以产生在输出端子处具有预充电电平的升压信号。 该电路还包括一个升压级，它被耦合以接收升压控制信号并在升压级输出端产生升压启动信号，该升压级输出端通过电容元件耦合到输出端。 当升压激活信号有效时，升压信号被设置为独立于电源电压的选定升压电平。

公开(公告)号：US06353566B1

公开(公告)日：2002-03-05

申请号：US09663552

申请日：2000-09-18

申请人： Takao Akaogi ,  Kazuhiro Kurihara ,  Thomas T. Shieh

发明人： Takao Akaogi ,  Kazuhiro Kurihara ,  Thomas T. Shieh

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C16/24 ,  G11C16/26

摘要： A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization pulse which is used to equalize the output stage of the sense amplifier to the input stage.

摘要翻译： 公开了一种用于可变工作电压高密度闪速存储器件的读出放大器输出均衡电路。 均衡电路通过可变地调节用于均衡感测放大器的输出级与输入级的均衡脉冲的持续时间来补偿由于变化的工作电压引起的变化的感测速度。

公开(公告)号：US06285627B1

公开(公告)日：2001-09-04

申请号：US09663909

申请日：2000-09-18

申请人： Kazuhiro Kurihara ,  Thomas T. Shieh

发明人： Kazuhiro Kurihara ,  Thomas T. Shieh

IPC分类号： G11C800

CPC分类号： G11C8/18 ,  G11C16/32

摘要： An equalization circuit for an address transition detector of a high density flash memory device is disclosed. The equalization circuit substantially equalizes the electrical characteristics of a particular signal path to those of another signal path wherein these signal paths transmit trigger signals which further generate other signals. The equalization ensures that resultant signals generated from the trigger signals which traverse these signal paths are generated in the same manner and with the same timing no matter which signal path the trigger signal travels down.

摘要翻译： 公开了一种用于高密度闪速存储器件的地址转换检测器的均衡电路。 均衡电路基本上将特定信号路径的电特性平衡到另一个信号路径的电特性，其中这些信号路径发送进一步产生其他信号的触发信号。 均衡确保从触发信号产生的横穿这些信号路径的结果信号以相同的方式和相同的定时产生，无论触发信号向哪个信号路径向下行进。