公开(公告)号：US07425498B2

公开(公告)日：2008-09-16

申请号：US11602293

申请日：2006-11-21

申请人： Satoshi Shimizu

发明人： Satoshi Shimizu

IPC分类号： H01L21/3213 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.

摘要翻译： 一种半导体器件包括：具有直线部分的栅极电极，位于直线部分延伸点上的虚拟电极，阻挡绝缘膜，侧壁绝缘膜，层间绝缘膜和延伸的线性接触部分 从上方观察，平行于直线部分。 当从上方观察时，由线性接触部分限定的矩形的长边位于侧壁绝缘膜之外并且位于栅电极和虚拟电极的顶部区域内。 当从上方观察时，在直线接触部分中出现的栅电极和虚拟电极之间的间隙G被填充有侧壁绝缘膜，使得半导体衬底不暴露。

公开(公告)号：US20080035985A1

公开(公告)日：2008-02-14

申请号：US11882164

申请日：2007-07-31

申请人： Satoshi Shimizu ,  Yoshihiro Ikeda

发明人： Satoshi Shimizu ,  Yoshihiro Ikeda

IPC分类号： H01L29/788 ,  H01L21/31

CPC分类号： H01L27/115 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11524

摘要： The semiconductor device which is hard to generate malfunction and whose reliability of an element is high, and its manufacturing method are offered.Each of a plurality of convex patterns is formed on the front surface of a semiconductor substrate so that it may have a floating gate and a control gate. The insulating layer has covered the side surface and the upper surface of a plurality of convex patterns, and the bottom between convex patterns. A contact interlayer insulating layer covers the cavity part located via an insulating layer between a plurality of convex patterns and on a plurality of convex patterns, and has a through hole. An insulating layer closes a through hole and occludes the cavity part.

摘要翻译： 难以产生故障，元件的可靠性高的半导体装置及其制造方法。 多个凸形图案中的每一个形成在半导体衬底的前表面上，使得其可以具有浮动栅极和控制栅极。 绝缘层已经覆盖了多个凸形图案的侧表面和上表面，以及凸起图案之间的底部。 接触层间绝缘层覆盖经由多个凸形图案之间的绝缘层和多个凸形图案上的绝缘层，并具有通孔。 绝缘层封闭通孔并封闭空腔部分。

公开(公告)号：US20070269949A1

公开(公告)日：2007-11-22

申请号：US11822467

申请日：2007-07-06

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L21/336

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US07289146B2

公开(公告)日：2007-10-30

申请号：US10766461

申请日：2004-01-27

申请人： Akio Saigusa ,  Satoshi Shimizu

发明人： Akio Saigusa ,  Satoshi Shimizu

IPC分类号： H04N9/64

CPC分类号： H04N5/359 ,  H04N1/1008 ,  H04N1/193 ,  H04N2201/0079 ,  H04N2201/0412

摘要： In an image reading apparatus using a solid state image pickup element, a smear amount and the total received light amount at whole image taking region of the CCD linear sensor when a light source is turned on without film, are measured and calculated.Using a ratio of the total received light amount when a light source is turned on without film to the one at the time of image reading, a smear correction data of each line is calculated for correction processing.

摘要翻译： 在使用固体摄像元件的图像读取装置中，测定并计算光源未被膜接通时CCD线性传感器的整个摄像区域的总体接收光量。 当光源在没有胶片的情况下打开时，使用总的接收光量的比例与图像读取时的总接收光量的比率，计算每行的涂片校正数据，以进行校正处理。

公开(公告)号：US20070209177A1

公开(公告)日：2007-09-13

申请号：US11796443

申请日：2007-04-27

申请人： Satoshi Shimizu ,  Masaru Matsuyama

发明人： Satoshi Shimizu ,  Masaru Matsuyama

IPC分类号： H01L41/22 ,  H01L41/00

CPC分类号： H03H9/1035 ,  H03H9/1021 ,  Y10T29/42 ,  Y10T29/49005

摘要： A small piezoelectric vibrator having low equivalent series resistance is realized. In the piezoelectric vibrator of the invention, a gettering substance for gettering inner gas is provided in a sealed space formed by a hermetic container where a piezoelectric vibrator piece is arranged. The gettering substance is formed on a surface of the piezoelectric vibrator piece or an inside wall of the hermetic container. A manufacturing process for the piezoelectric vibrator includes a process in which the gettering substance is provided inside the hermetic container which contains the piezoelectric vibrator piece inside the hermetic container, a process in which the hermetic container is hermetic-sealed so that the piezoelectric vibrator piece is sealed in the hermetic container, and a process in which the gettering substance is heated by a laser beam from outside to perform gettering of the inner gas of the hermetic container.

摘要翻译： 实现了具有低等效串联电阻的小型压电振动器。 在本发明的压电振动器中，用于吸入内部气体的吸气物质设置在由设置有压电振动片的密封容器形成的密封空间中。 吸气物质形成在压电振动片的表面或密封容器的内壁上。 压电振动器的制造方法包括在气密容器内含有压电振动片的密封容器内部设置吸气物质的方法，将密封容器密封地密封，使得压电振动片为 密封在密封容器中，并且其中通过来自外部的激光束加热吸气物质以进行密封容器的内部气体的吸气的过程。

公开(公告)号：US20070205457A1

公开(公告)日：2007-09-06

申请号：US11797406

申请日：2007-05-03

申请人： Satoshi Shimizu

发明人： Satoshi Shimizu

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

公开(公告)号：US07212047B2

公开(公告)日：2007-05-01

申请号：US11241995

申请日：2005-10-04

申请人： Yasuyuki Kimura ,  Satoshi Shimizu ,  Masakatsu Yokota ,  Ken Suyama ,  Aleksander Dec

发明人： Yasuyuki Kimura ,  Satoshi Shimizu ,  Masakatsu Yokota ,  Ken Suyama ,  Aleksander Dec

IPC分类号： H03L7/06

CPC分类号： H03L7/0893 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1075

摘要： A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

公开(公告)号：US07154132B2

公开(公告)日：2006-12-26

申请号：US10716614

申请日：2003-11-20

申请人： Satoshi Shimizu

发明人： Satoshi Shimizu

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a gate electrode having a straight portion, a dummy electrode located at a point on the extension of the straight portion, a stopper insulating film, a sidewall insulating film, an interlayer insulating film, and a linear contact portion extending, when viewed from above, parallel to the straight portion. The longer side of the rectangle defined by the linear contact portion is, when viewed from above, located beyond the sidewall insulating film and within the top region of the gate electrode and the dummy electrode. A gap G between the gate electrode and the dummy electrode appearing, when viewed from above, in the linear contact portion is filled with the sidewall insulating film such that the semiconductor substrate is not exposed.

摘要翻译： 一种半导体器件包括：具有直线部分的栅极电极，位于直线部分延伸点上的虚拟电极，阻挡绝缘膜，侧壁绝缘膜，层间绝缘膜和延伸的线性接触部分 从上方观察，平行于直线部分。 当从上方观察时，由线性接触部分限定的矩形的长边位于侧壁绝缘膜之外并且位于栅电极和虚拟电极的顶部区域内。 当从上方观察时，在直线接触部分中出现的栅电极和虚拟电极之间的间隙G被填充有侧壁绝缘膜，使得半导体衬底不暴露。

公开(公告)号：US20060028255A1

公开(公告)日：2006-02-09

申请号：US11241995

申请日：2005-10-04

申请人： Yasuyuki Kimura ,  Satoshi Shimizu ,  Masakatsu Yokota ,  Ken Suyama ,  Aleksander Dec

发明人： Yasuyuki Kimura ,  Satoshi Shimizu ,  Masakatsu Yokota ,  Ken Suyama ,  Aleksander Dec

IPC分类号： H03L7/06

CPC分类号： H03L7/0893 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1075

摘要： A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

公开(公告)号：US20050275063A1

公开(公告)日：2005-12-15

申请号：US10617667

申请日：2003-07-14

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/115

摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.

摘要翻译： 半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。 由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。