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    Semiconductor device and method of manufacturing the same
    1.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20080035985A1

    公开(公告)日：2008-02-14

    申请号：US11882164

    申请日：2007-07-31

    申请人： Satoshi Shimizu ,  Yoshihiro Ikeda

    发明人： Satoshi Shimizu ,  Yoshihiro Ikeda

    IPC分类号： H01L29/788 ,  H01L21/31

    CPC分类号： H01L27/115 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11524

    摘要： The semiconductor device which is hard to generate malfunction and whose reliability of an element is high, and its manufacturing method are offered.Each of a plurality of convex patterns is formed on the front surface of a semiconductor substrate so that it may have a floating gate and a control gate. The insulating layer has covered the side surface and the upper surface of a plurality of convex patterns, and the bottom between convex patterns. A contact interlayer insulating layer covers the cavity part located via an insulating layer between a plurality of convex patterns and on a plurality of convex patterns, and has a through hole. An insulating layer closes a through hole and occludes the cavity part.

    摘要翻译： 难以产生故障，元件的可靠性高的半导体装置及其制造方法。 多个凸形图案中的每一个形成在半导体衬底的前表面上，使得其可以具有浮动栅极和控制栅极。 绝缘层已经覆盖了多个凸形图案的侧表面和上表面，以及凸起图案之间的底部。 接触层间绝缘层覆盖经由多个凸形图案之间的绝缘层和多个凸形图案上的绝缘层，并具有通孔。 绝缘层封闭通孔并封闭空腔部分。

    Braking force control system for vehicle
    2.
    发明授权
    Braking force control system for vehicle 有权

    公开(公告)号：US09789861B2

    公开(公告)日：2017-10-17

    申请号：US14232156

    申请日：2012-07-13

    申请人： Satoshi Shimizu

    发明人： Satoshi Shimizu

    IPC分类号： B60T8/24 ,  B60T8/1764 ,  B60T8/26

    CPC分类号： B60T8/246 ,  B60T8/1764 ,  B60T8/26

    摘要： In a braking force control system for a vehicle having a braking system capable of controlling braking force of each of right and left front wheels and right and left rear wheels independently of one another, when anti-skid control starts being performed on one of the front wheels while the vehicle is running on a road having different coefficients of friction on the left side and right side thereof, increase of the braking force of the other front wheel laterally opposite to the above-indicated one front wheel is suppressed, and increase of the braking force of at least one of the right and left rear wheels is suppressed.

    Nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08339862B2

    公开(公告)日：2012-12-25

    申请号：US12343552

    申请日：2008-12-24

    申请人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

    发明人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

    IPC分类号： G11C16/06 ,  G11C11/34 ,  H01L29/792

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/12 ,  H01L27/115 ,  H01L27/11524

    摘要： According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

    摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储器件，包括：沿第一方向布置的多个位线; 沿所述第一方向布置的多条源极线，所述多条源极线与所述多个位线平行，所述多个源极线与所述多个位线不同; 沿垂直于第一方向的第二方向布置的多个存储栅极线; 多个存储单元，以矩阵形式布置，所述多个存储单元中的每一个包括具有第一端子，第二端子，第一端子和第二端子之间的通道的ap型MIS非易失性晶体管，形成在栅极绝缘膜上的栅极绝缘膜 连接到所述多个存储栅极线中的一个对应的存储栅极线的栅极，以及形成在所述栅极绝缘膜和所述栅电极之间的载流子存储层，所述第一端子连接到所述多个栅极线中的一个相应的位线 位线，并且所述第二端子连接到所述多个源极线中的一个对应的源极线。

    Non-volatile semiconductor memory device
    8.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08106443B2

    公开(公告)日：2012-01-31

    申请号：US12246193

    申请日：2008-10-06

    申请人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

    发明人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11568 ,  G11C16/0441 ,  G11C16/0491 ,  H01L21/26586 ,  H01L29/792

    摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

    摘要翻译： 非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部 所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层， 形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散 肋骨中的结构是不对称的。