公开(公告)号：US20070189106A1

公开(公告)日：2007-08-16

申请号：US11648903

申请日：2007-01-03

Applicant: Christopher Johnson ,  Scott Schaefer

Inventor： Christopher Johnson ,  Scott Schaefer

IPC: G11C8/00

CPC classification number: G11C7/225 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/2227

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

Abstract translation: 本发明提供一种存储器件，其具有具有可选位的模式寄存器，该可选位将存储器件设置为使用多个可能的时钟输入信号（例如单个时钟输入或差分时钟输入）中选定的一个进行操作。

公开(公告)号：US20070002663A1

公开(公告)日：2007-01-04

申请号：US11516848

申请日：2006-09-07

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/143 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract translation: 用于降低存储器件消耗的功率的装置选择性地启动在有功断电操作模式期间可以暂停延迟补偿电路的操作的功率节省模式。

公开(公告)号：US20060123221A1

公开(公告)日：2006-06-08

申请号：US11338155

申请日：2006-01-24

Applicant: Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

Inventor： Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

IPC: G06F15/177

CPC classification number: G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

Abstract: Methods of configuring a system. More specifically, operating current values corresponding to respective memory devices of memory module may be stored in programmable elements, such as antifuses, located on the memory device, during fabrication. The operating current values may be read from and/or stored in a non-volatile memory device on the memory module. Once the memory module is incorporated into a system, the programmable elements on the memory devices and/or the non-volatile memory device on the memory module may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.

Abstract translation: 配置系统的方法 更具体地，对应于存储器模块的各个存储器件的工作电流值可以在制造期间存储在位于存储器件上的可编程元件，例如反熔丝。 操作电流值可以从存储器模块中的非易失性存储器件读取和/或存储在存储器模块中的非易失性存储器件中。 一旦存储器模块被并入到系统中，可以访问存储器模块上的可编程元件和/或存储器模块上的非易失性存储器设备，使得可以将系统配置为根据工作电流值进行最佳操作 测量系统中的每个存储设备。

公开(公告)号：US20060062056A1

公开(公告)日：2006-03-23

申请号：US11270578

申请日：2005-11-10

Applicant: Christopher Johnson ,  Scott Schaefer

Inventor： Christopher Johnson ,  Scott Schaefer

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C7/225 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/2227

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

公开(公告)号：US06862202B2

公开(公告)日：2005-03-01

申请号：US10669663

申请日：2003-09-23

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C7/22 ,  G11C8/12 ,  G11C5/02

CPC classification number: G11C7/22 ,  G11C8/12

Abstract: A memory module for an electronic device provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract translation: 用于电子设备的存储器模块提供用于减少访问所需数量的数据位所需的功率量的装置。 这提供了存储器模块的设计，其在读取或写入周期期间比当前模块设计要求更少的DRAM被接通，从而使用更少的功率。

公开(公告)号：US06819599B2

公开(公告)日：2004-11-16

申请号：US10210483

申请日：2002-08-01

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C700

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

Abstract: A method and apparatus are provided for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract translation: 提供了一种方法和装置，用于通过将定义的一组位加载到存储器的一个或多个寄存器中来对存储器中的数据选通（DQS）前导码进行编程，其中一个或多个位被格式化以用于启用数据选通前导码。 这些位中的至少一个用于使数据选通前同步码作为存储器的默认数据选通前导码，或者作为缩减数据选通前导，其时间长度设置为等于默认前导码的一部分或时钟的一部分 周期。 使能位可以用于提供用于产生延迟的输入，该延迟向存储器的驱动器提供延迟的信号，用于产生减少的数据选通前导码，并用于排序或驱动要从存储器读出的数据。 缩减数据选通前导码也可用于将数据写入存储器。

公开(公告)号：US06693837B2

公开(公告)日：2004-02-17

申请号：US10128936

申请日：2002-04-23

Applicant: Scott Schaefer ,  Todd D. Farrell

Inventor： Scott Schaefer ,  Todd D. Farrell

IPC: G11C700

CPC classification number: G11C11/406

Abstract: A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.

Abstract translation: 公开了一种系统和方法，用于向当前在DRAM设备中使用的自刷新控制逻辑添加逻辑，以确保在自刷新模式和操作模式之间的转换时，在刷新期间至少一行存储器单元被刷新 发布转换命令后的等待状态。 在此现有等待状态期间执行此刷新消除了在强制刷新间隔内刷新行是否已被刷新以及完成转换后执行至少一行自动刷新所需的时间的担忧。

公开(公告)号：US06665219B2

公开(公告)日：2003-12-16

申请号：US10199130

申请日：2002-07-22

Applicant: Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

Inventor： Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

IPC: G11C700

CPC classification number: G11C5/14

Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

公开(公告)号：US06438060B1

公开(公告)日：2002-08-20

申请号：US09780606

申请日：2001-02-12

Applicant: Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

Inventor： Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

IPC: G11C700

CPC classification number: G11C5/14

Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

Abstract translation: 一种用于在断电模式操作期间通过中断延迟线的时钟转换来降低存储器集成电路的功耗的装置和方法。 存储器集成电路可以包括延迟锁定环，其包括串联连接并且适于延迟自由运行时钟的信号的传播的多个延迟元件。 当不需要延迟信号时，如在断电模式操作期间，防止自由运行的时钟信号到达延迟锁定环路。 因此，延迟元件不切换，并且节省与延迟元件切换相关联的功率。

公开(公告)号：US5905909A

公开(公告)日：1999-05-18

申请号：US783379

申请日：1997-01-13

Applicant: Brett Williams ,  Scott Schaefer

Inventor： Brett Williams ,  Scott Schaefer

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4072 ,  G11C11/4096 ,  G06F13/00

CPC classification number: G11C5/066 ,  G11C11/4072 ,  G11C11/4096 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1072

Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.

Abstract translation: 一种具有用于接收第一命令和第二命令并具有初始化和重新编程电路的主控制电路的同步动态随机存取存储器（SDRAM）装置。 主控制电路响应于第一命令产生和初始化信号，并且响应于第二命令产生重编程信号。 初始化和重编程电路响应于初始化信号以控制控制操作特征的初始编程，并响应重编程信号以控制控制操作特征的重新编程。